| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 67.190us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 47.658us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 55.588us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 2.000s | 35.542us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 34.428us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 3.000s | 272.163us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 55.588us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 34.428us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 12.000s | 2799.951us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 7.000s | 342.244us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 37.000s | 928.364us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 236.000s | 8795.165us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 11.000s | 510.290us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 34.000s | 1939.389us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 9032.586us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 3977.363us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 111.489us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 558.000s | 189650.848us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 36.978us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 3.000s | 73.402us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 2.000s | 147.412us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 11.000s | 1964.289us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 6.000s | 49.284us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 67.190us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 3.000s | 111.489us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 34.000s | 1939.389us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 58.000s | 8321.779us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 15.309us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 7.000s | 147.651us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 7.000s | 147.651us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 47.658us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 55.588us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 34.428us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 51.010us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 47.658us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 55.588us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 34.428us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 51.010us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 1730.814us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 810.985us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 191.929us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 810.985us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 191.929us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 11.000s | 1964.289us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 11.000s | 1964.289us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 55.588us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 3977.363us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 3977.363us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 3977.363us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 9032.586us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 1730.814us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3602.088s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 67.190us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 67.190us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 3977.363us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 810.985us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 9032.586us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 810.985us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 810.985us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 67.190us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 810.985us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 58.000s | 12554.289us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 41970416952939880158278731535635917770617052585826728729567153638272957986904 | None | ||
| sram_ctrl_mubi_enc_err | 52059873933421602202126080158428409597249530632128515384004263289752558703716 | None | ||
| sram_ctrl_readback_err | 57768397735094122495781238017584142796276931127767409247478233135232672526950 | None | ||
| sram_ctrl_mubi_enc_err | 41017688215185292607771677778379231214833715346746071086740357155835988263435 | None | ||
| sram_ctrl_readback_err | 96035613801679500158039177825276339722542338729405288849802542055211454799663 | None | ||
| sram_ctrl_mubi_enc_err | 91241917264530497621916686611088831275945022006600141128881160443199607180897 | None | ||
| sram_ctrl_readback_err | 81437470097102200958700321552827589389822981571882352725174369969739504365102 | None | ||
| sram_ctrl_mubi_enc_err | 72630209813045523025231422342047610743498417281427510383171300497803020731657 | None | ||
| sram_ctrl_readback_err | 51686191454517906313601875695005298127006901492637522735481540833798870799584 | None | ||
| sram_ctrl_mubi_enc_err | 84914438083810811310136824408632049770087042772089807452587526466701876902067 | None | ||
| sram_ctrl_readback_err | 30343608723156972201767937632183976386238450802039929423659660155785643702193 | None | ||
| sram_ctrl_mubi_enc_err | 92851913681451163647570723353311408091952050629248874161785043505683983764909 | None | ||
| sram_ctrl_readback_err | 62111464417966389255003531125114280461374129203262019692901607794348925865504 | None | ||
| sram_ctrl_mubi_enc_err | 38872035212233320437159658017002505372349515742668696114194778312385906256618 | None | ||
| sram_ctrl_readback_err | 80589374825212241077004530095485595209893366498938358747605445822860034496050 | None | ||
| sram_ctrl_mubi_enc_err | 27901564334233692641760839640025740967583899983733594385043719194036929762316 | None | ||