Simulation Results: adc_ctrl

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.35 %
  • code
  • 98.00 %
  • assert
  • 96.76 %
  • func
  • 19.29 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 95.12 %
  • toggle
  • 100.00 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
adc_ctrl_smoke 18.770s 5858.775us 10 10 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.420s 583.563us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 2.480s 543.966us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 41.260s 52895.064us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.700s 608.593us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.800s 508.961us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 2.480s 543.966us 5 5 100.00
adc_ctrl_csr_aliasing 1.700s 608.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 10 10 100.00
adc_ctrl_filters_polled 153.540s 54351.751us 10 10 100.00
filters_polled_fixed 10 10 100.00
adc_ctrl_filters_polled_fixed 95.310s 34613.413us 10 10 100.00
filters_interrupt 10 10 100.00
adc_ctrl_filters_interrupt 133.810s 54244.649us 10 10 100.00
filters_interrupt_fixed 10 10 100.00
adc_ctrl_filters_interrupt_fixed 155.820s 54452.361us 10 10 100.00
filters_wakeup 10 10 100.00
adc_ctrl_filters_wakeup 206.240s 74537.873us 10 10 100.00
filters_wakeup_fixed 10 10 100.00
adc_ctrl_filters_wakeup_fixed 190.540s 74486.166us 10 10 100.00
filters_both 10 10 100.00
adc_ctrl_filters_both 150.460s 57769.920us 10 10 100.00
clock_gating 10 10 100.00
adc_ctrl_clock_gating 47.150s 43406.063us 10 10 100.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 13.320s 3637.853us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 127.260s 41283.645us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 307.520s 119275.750us 10 10 100.00
stress_all 10 10 100.00
adc_ctrl_stress_all 575.040s 245186.196us 10 10 100.00
alert_test 10 10 100.00
adc_ctrl_alert_test 2.000s 420.123us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 2.350s 531.925us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 4.320s 334.527us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 4.320s 334.527us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 1.420s 583.563us 1 1 100.00
adc_ctrl_csr_rw 2.480s 543.966us 5 5 100.00
adc_ctrl_csr_aliasing 1.700s 608.593us 1 1 100.00
adc_ctrl_same_csr_outstanding 12.920s 4373.243us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 1.420s 583.563us 1 1 100.00
adc_ctrl_csr_rw 2.480s 543.966us 5 5 100.00
adc_ctrl_csr_aliasing 1.700s 608.593us 1 1 100.00
adc_ctrl_same_csr_outstanding 12.920s 4373.243us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 28 30 93.33
adc_ctrl_sec_cm 18.710s 7355.791us 5 5 100.00
adc_ctrl_tl_intg_err 27.300s 8880.312us 23 25 92.00
sec_cm_bus_integrity 23 25 92.00
adc_ctrl_tl_intg_err 27.300s 8880.312us 23 25 92.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
adc_ctrl_stress_all_with_rand_reset 110.070s 855390.955us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [adc_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 2 test runs
adc_ctrl_tl_intg_err 97559766756184249435328873334020216493422050818319592346700363320215652626442 425
UVM_INFO @ 1217576387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_tl_intg_err 60009864841489110725568403232498697466851382334346897872362040492694811207794 407
UVM_INFO @ 824965929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---