Simulation Results: aon_timer

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.09 %
  • code
  • 99.17 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • line
  • 99.09 %
  • branch
  • 98.56 %
  • cond
  • 99.05 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
aon_timer_smoke 2.390s 654.371us 5 5 100.00
csr_hw_reset 1 1 100.00
aon_timer_csr_hw_reset 3.100s 1099.589us 1 1 100.00
csr_rw 5 5 100.00
aon_timer_csr_rw 1.930s 475.902us 5 5 100.00
csr_bit_bash 1 1 100.00
aon_timer_csr_bit_bash 19.840s 10829.382us 1 1 100.00
csr_aliasing 1 1 100.00
aon_timer_csr_aliasing 1.360s 533.348us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aon_timer_csr_mem_rw_with_rand_reset 1.680s 330.751us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aon_timer_csr_rw 1.930s 475.902us 5 5 100.00
aon_timer_csr_aliasing 1.360s 533.348us 1 1 100.00
mem_walk 1 1 100.00
aon_timer_mem_walk 1.580s 412.940us 1 1 100.00
mem_partial_access 1 1 100.00
aon_timer_mem_partial_access 1.450s 265.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
prescaler 15 15 100.00
aon_timer_prescaler 62.730s 49579.491us 15 15 100.00
jump 5 5 100.00
aon_timer_jump 2.610s 721.726us 5 5 100.00
stress_all 15 15 100.00
aon_timer_stress_all 214.840s 141271.814us 15 15 100.00
alert_test 10 10 100.00
aon_timer_alert_test 1.680s 495.236us 10 10 100.00
intr_test 10 10 100.00
aon_timer_intr_test 1.660s 337.794us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aon_timer_tl_errors 4.260s 614.297us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aon_timer_tl_errors 4.260s 614.297us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aon_timer_csr_hw_reset 3.100s 1099.589us 1 1 100.00
aon_timer_csr_rw 1.930s 475.902us 5 5 100.00
aon_timer_csr_aliasing 1.360s 533.348us 1 1 100.00
aon_timer_same_csr_outstanding 9.250s 2329.281us 5 5 100.00
tl_d_partial_access 12 12 100.00
aon_timer_csr_hw_reset 3.100s 1099.589us 1 1 100.00
aon_timer_csr_rw 1.930s 475.902us 5 5 100.00
aon_timer_csr_aliasing 1.360s 533.348us 1 1 100.00
aon_timer_same_csr_outstanding 9.250s 2329.281us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 27 30 90.00
aon_timer_sec_cm 9.340s 3995.255us 5 5 100.00
aon_timer_tl_intg_err 19.830s 8845.315us 22 25 88.00
sec_cm_bus_integrity 22 25 88.00
aon_timer_tl_intg_err 19.830s 8845.315us 22 25 88.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_threshold 5 5 100.00
aon_timer_smoke_max_thold 1.560s 562.590us 5 5 100.00
min_threshold 5 5 100.00
aon_timer_smoke_min_thold 1.900s 724.678us 5 5 100.00
wkup_count_hi_cdc 5 5 100.00
aon_timer_wkup_count_cdc_hi 10.400s 3794.884us 5 5 100.00
custom_intr 10 10 100.00
aon_timer_custom_intr 2.260s 641.537us 10 10 100.00
alternating_on_off 5 5 100.00
aon_timer_alternating_enable_on_off 19.910s 4221.547us 5 5 100.00
stress_all_with_rand_reset 15 15 100.00
aon_timer_stress_all_with_rand_reset 39.510s 24098.494us 15 15 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [aon_timer_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 3 test runs
aon_timer_tl_intg_err 91266181966425217670601160344286576840068967564905564136132089295656264642783 189
UVM_INFO @ 5511616208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aon_timer_tl_intg_err 50439930862033112408753148836985688609050517026495850855071680469394498621026 199
UVM_INFO @ 6516906248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aon_timer_tl_intg_err 17987150981451954353500024762039180635005909268570362327239451276219471765147 243
UVM_INFO @ 7568731611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---