Simulation Results: chip

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.16 %
  • code
  • 77.39 %
  • assert
  • 97.28 %
  • func
  • 98.80 %
  • line
  • 94.09 %
  • branch
  • 94.61 %
  • cond
  • 92.92 %
  • toggle
  • 72.02 %
  • FSM
  • 33.33 %
Validation stages
V1
99.20%
V2
87.69%
V2S
83.33%
V3
82.69%
unmapped
13.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 9 9 100.00
chip_sw_example_rom 173.220s 2348.525us 3 3 100.00
chip_sw_example_manufacturer 289.460s 2651.471us 3 3 100.00
chip_sw_example_concurrency 326.070s 2980.327us 3 3 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 892.290s 11569.277us 1 1 100.00
csr_rw 5 5 100.00
chip_csr_rw 900.580s 11794.766us 5 5 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 713.950s 9800.498us 1 1 100.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 10800.213s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 5 5 100.00
chip_csr_mem_rw_with_rand_reset 1279.400s 12091.893us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 5 6 83.33
chip_csr_aliasing 10800.213s 0.000us 0 1 0.00
chip_csr_rw 900.580s 11794.766us 5 5 100.00
xbar_smoke 50 50 100.00
xbar_smoke 11.810s 243.629us 50 50 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 570.950s 4063.146us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 570.950s 4063.146us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 570.950s 4063.146us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 665.020s 3948.326us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 665.020s 3948.326us 5 5 100.00
chip_sw_uart_tx_rx_idx1 722.950s 4282.046us 5 5 100.00
chip_sw_uart_tx_rx_idx2 646.190s 4086.611us 5 5 100.00
chip_sw_uart_tx_rx_idx3 648.700s 4624.227us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 3645.730s 12836.697us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 3556.610s 12584.071us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1689.360s 13075.058us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 9 10 90.00
chip_padctrl_attributes 735.250s 11552.266us 9 10 90.00
chip_padctrl_attributes 9 10 90.00
chip_padctrl_attributes 735.250s 11552.266us 9 10 90.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 369.920s 3017.207us 3 3 100.00
chip_sw_sleep_pin_wake 2 3 66.67
chip_sw_sleep_pin_wake 586.650s 5767.306us 2 3 66.67
chip_sw_sleep_pin_retention 0 3 0.00
chip_sw_sleep_pin_retention 307.800s 3128.149us 0 3 0.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1670.280s 11550.116us 5 5 100.00
chip_tap_straps_testunlock0 1000.000s 9183.668us 5 5 100.00
chip_tap_straps_rma 735.760s 5721.867us 5 5 100.00
chip_tap_straps_prod 2402.030s 15285.698us 5 5 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 757.630s 5001.624us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 757.630s 5001.624us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 989.870s 6648.574us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 3684.780s 14479.098us 0 3 0.00
chip_sw_ast_sys_clk_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6410.140s 20090.482us 3 3 100.00
chip_sw_aes_enc_jitter_en 403.900s 3131.186us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1306.520s 6809.030us 3 3 100.00
chip_sw_hmac_enc_jitter_en 309.090s 2830.879us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 3366.960s 13366.278us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 370.430s 2921.382us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 691.170s 4743.450us 3 3 100.00
chip_sw_clkmgr_jitter 276.420s 2964.516us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 379.640s 2828.109us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 5 8 62.50
chip_sw_sensor_ctrl_alert 1062.580s 7827.689us 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 255.430s 3018.778us 0 3 0.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 368.970s 3042.939us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 0 3 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 255.430s 3018.778us 0 3 0.00
chip_sw_smoketest 48 48 100.00
chip_sw_aes_smoketest 421.190s 2969.487us 3 3 100.00
chip_sw_aon_timer_smoketest 373.710s 2658.384us 3 3 100.00
chip_sw_clkmgr_smoketest 300.600s 2225.016us 3 3 100.00
chip_sw_csrng_smoketest 257.970s 2163.403us 3 3 100.00
chip_sw_entropy_src_smoketest 1498.030s 7206.014us 3 3 100.00
chip_sw_gpio_smoketest 366.060s 2800.036us 3 3 100.00
chip_sw_hmac_smoketest 393.370s 2904.717us 3 3 100.00
chip_sw_kmac_smoketest 375.870s 3020.674us 3 3 100.00
chip_sw_otbn_smoketest 2593.430s 11220.387us 3 3 100.00
chip_sw_pwrmgr_smoketest 520.250s 5908.316us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 583.850s 5679.696us 3 3 100.00
chip_sw_rv_plic_smoketest 293.130s 3416.832us 3 3 100.00
chip_sw_rv_timer_smoketest 372.200s 2886.964us 3 3 100.00
chip_sw_rstmgr_smoketest 262.120s 2546.889us 3 3 100.00
chip_sw_sram_ctrl_smoketest 278.650s 2756.969us 3 3 100.00
chip_sw_uart_smoketest 292.590s 3175.896us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 317.910s 2462.749us 3 3 100.00
chip_sw_rom_functests 3 3 100.00
rom_keymgr_dpe_functest 663.430s 4357.887us 3 3 100.00
chip_sw_boot 0 3 0.00
chip_sw_uart_tx_rx_bootstrap 28800.430s 0.000us 0 3 0.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 5871.710s 15310.984us 3 3 100.00
chip_sw_rom_raw_unlock 2 3 66.67
rom_raw_unlock 1859.600s 20201.934us 2 3 66.67
chip_sw_power_idle_load 3 3 100.00
chip_sw_power_idle_load 663.710s 4222.883us 3 3 100.00
chip_sw_power_sleep_load 2 3 66.67
chip_sw_power_sleep_load 587.890s 10043.838us 2 3 66.67
chip_sw_exit_test_unlocked_bootstrap 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 13200.229s 0.000us 0 3 0.00
tl_d_oob_addr_access 23 30 76.67
chip_tl_errors 3600.183s 0.000us 23 30 76.67
tl_d_illegal_access 23 30 76.67
chip_tl_errors 3600.183s 0.000us 23 30 76.67
tl_d_outstanding_access 10 12 83.33
chip_csr_aliasing 10800.213s 0.000us 0 1 0.00
chip_same_csr_outstanding 5765.860s 31861.857us 4 5 80.00
chip_csr_hw_reset 892.290s 11569.277us 1 1 100.00
chip_csr_rw 900.580s 11794.766us 5 5 100.00
tl_d_partial_access 10 12 83.33
chip_csr_aliasing 10800.213s 0.000us 0 1 0.00
chip_same_csr_outstanding 5765.860s 31861.857us 4 5 80.00
chip_csr_hw_reset 892.290s 11569.277us 1 1 100.00
chip_csr_rw 900.580s 11794.766us 5 5 100.00
xbar_base_random_sequence 50 50 100.00
xbar_random 77.680s 1889.888us 50 50 100.00
xbar_random_delay 300 300 100.00
xbar_smoke_zero_delays 7.630s 51.381us 50 50 100.00
xbar_smoke_large_delays 108.200s 10104.001us 50 50 100.00
xbar_smoke_slow_rsp 103.730s 6242.280us 50 50 100.00
xbar_random_zero_delays 51.260s 510.846us 50 50 100.00
xbar_random_large_delays 471.680s 51786.353us 50 50 100.00
xbar_random_slow_rsp 432.610s 30445.195us 50 50 100.00
xbar_unmapped_address 100 100 100.00
xbar_unmapped_addr 51.550s 910.286us 50 50 100.00
xbar_error_and_unmapped_addr 77.060s 1353.720us 50 50 100.00
xbar_error_cases 100 100 100.00
xbar_error_random 75.770s 1604.039us 50 50 100.00
xbar_error_and_unmapped_addr 77.060s 1353.720us 50 50 100.00
xbar_all_access_same_device 100 100 100.00
xbar_access_same_device 152.960s 3397.337us 50 50 100.00
xbar_access_same_device_slow_rsp 1102.200s 86247.206us 50 50 100.00
xbar_all_hosts_use_same_source_id 50 50 100.00
xbar_same_source 87.140s 2440.303us 50 50 100.00
xbar_stress_all 100 100 100.00
xbar_stress_all 597.020s 14446.924us 50 50 100.00
xbar_stress_all_with_error 470.030s 12443.681us 50 50 100.00
xbar_stress_with_reset 100 100 100.00
xbar_stress_all_with_rand_reset 729.510s 11334.045us 50 50 100.00
xbar_stress_all_with_reset_error 627.190s 16695.224us 50 50 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 5871.710s 15310.984us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 5619.980s 26575.773us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 6407.270s 29141.956us 3 3 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 4166.040s 11561.064us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 5963.580s 16471.628us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 5662.870s 15803.157us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 5593.810s 15794.953us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 5551.450s 15936.411us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 4034.020s 13018.266us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 5785.400s 16313.742us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 5600.340s 16945.814us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 5767.690s 17629.551us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 5534.520s 15823.617us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 7505.270s 17631.322us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 9752.660s 24303.786us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 9992.710s 25513.307us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 10170.580s 24771.952us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 9637.080s 24430.995us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 7119.100s 17612.489us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 9456.950s 27722.775us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 9877.440s 27935.476us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 9325.650s 22536.631us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 9739.400s 28149.984us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 3777.740s 9991.518us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 5740.980s 18632.874us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 6048.510s 22826.047us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 6357.450s 26503.107us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 6375.410s 25361.447us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 3717.130s 10879.404us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 6094.300s 23000.159us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 5692.050s 21422.568us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 6283.720s 24263.781us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 5933.680s 22888.655us 1 1 100.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 4118.060s 11249.482us 3 3 100.00
rom_e2e_asm_init_dev 6068.550s 15410.982us 3 3 100.00
rom_e2e_asm_init_prod 6016.040s 15669.758us 3 3 100.00
rom_e2e_asm_init_prod_end 5918.800s 15843.514us 3 3 100.00
rom_e2e_asm_init_rma 5753.420s 17479.088us 3 3 100.00
rom_e2e_keymgr_dpe_init 9 9 100.00
rom_e2e_keymgr_dpe_init_rom_ext_meas 11443.310s 28994.942us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_no_meas 11833.540s 30090.636us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas 11253.830s 30428.676us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 6112.470s 16475.748us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.185s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.185s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 383.740s 3094.371us 3 3 100.00
chip_sw_aes_enc_jitter_en 403.900s 3131.186us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 259.070s 2879.827us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 339.860s 2294.582us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 2365.760s 10992.443us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 330.310s 3037.324us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 695.050s 4753.411us 3 3 100.00
chip_sw_all_escalation_resets 93 100 93.00
chip_sw_all_escalation_resets 810.360s 4940.246us 93 100 93.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 896.810s 4737.923us 3 3 100.00
chip_plic_all_irqs_10 560.060s 3489.110us 3 3 100.00
chip_plic_all_irqs_20 670.230s 3624.670us 3 3 100.00
chip_sw_alert_handler_entropy 0 3 0.00
chip_sw_alert_handler_entropy 401.110s 3222.031us 0 3 0.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 2239.400s 12497.006us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 729.370s 5432.038us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 441.370s 3043.773us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 379.540s 2983.113us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2139.160s 8015.099us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1898.680s 7393.172us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1315.990s 8294.542us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 3 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 14400.197s 0.000us 0 3 0.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 403.080s 4053.983us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 520.250s 5908.316us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 403.080s 4053.983us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1031.970s 8324.562us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1031.970s 8324.562us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 605.150s 7000.073us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 670.220s 5071.252us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 1045.520s 6004.582us 3 3 100.00
chip_sw_aes_idle 339.860s 2294.582us 3 3 100.00
chip_sw_hmac_enc_idle 388.800s 2804.578us 3 3 100.00
chip_sw_kmac_idle 333.800s 3230.734us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 553.760s 4475.309us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 449.130s 4777.508us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 425.520s 4370.084us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 549.380s 4167.385us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1460.740s 11599.578us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 698.960s 4319.977us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 723.410s 4614.311us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 676.290s 4500.299us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 636.480s 4822.256us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 639.420s 3998.467us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 696.630s 4936.357us 3 3 100.00
chip_sw_ast_clk_outputs 989.870s 6648.574us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 2690.940s 28550.023us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 676.290s 4500.299us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 636.480s 4822.256us 3 3 100.00
chip_sw_clkmgr_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6410.140s 20090.482us 3 3 100.00
chip_sw_aes_enc_jitter_en 403.900s 3131.186us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1306.520s 6809.030us 3 3 100.00
chip_sw_hmac_enc_jitter_en 309.090s 2830.879us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 3366.960s 13366.278us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 370.430s 2921.382us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 691.170s 4743.450us 3 3 100.00
chip_sw_clkmgr_jitter 276.420s 2964.516us 3 3 100.00
chip_sw_clkmgr_extended_range 24 24 100.00
chip_sw_clkmgr_jitter_reduced_freq 278.860s 3342.902us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 6890.860s 26156.196us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 316.890s 3028.811us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 312.720s 3118.716us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 2134.810s 12658.867us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 367.080s 3318.441us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 549.910s 4448.882us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 7575.290s 31909.612us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 989.870s 6648.574us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 0 3 0.00
chip_sw_clkmgr_sleep_frequency 653.090s 4329.938us 0 3 0.00
chip_sw_clkmgr_reset_frequency 0 3 0.00
chip_sw_clkmgr_reset_frequency 819.360s 11285.142us 0 3 0.00
chip_sw_clkmgr_escalation_reset 93 100 93.00
chip_sw_all_escalation_resets 810.360s 4940.246us 93 100 93.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2139.160s 8015.099us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 4354.820s 24012.615us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 548.780s 4011.424us 3 3 100.00
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 1127.930s 8211.320us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 400.560s 2735.426us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 11501.170s 32490.548us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 320.810s 2722.298us 3 3 100.00
chip_sw_edn_entropy_reqs 1438.900s 6954.352us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 320.810s 2722.298us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 4354.820s 24012.615us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 290.140s 2402.697us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 313.330s 2702.265us 3 3 100.00
chip_sw_hmac_enc_jitter_en 309.090s 2830.879us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 388.800s 2804.578us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 2006.940s 10174.841us 3 3 100.00
chip_sw_hmac_multistream_mode 0 3 0.00
chip_sw_hmac_multistream 3043.250s 12010.100us 0 3 0.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 716.130s 4428.430us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 783.030s 5604.155us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 763.870s 5162.910us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 571.490s 4179.072us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 6 6 100.00
chip_sw_keymgr_dpe_key_derivation 2763.080s 10715.968us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 3366.960s 13366.278us 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 2529.690s 10836.558us 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 2365.760s 10992.443us 3 3 100.00
chip_sw_keymgr_dpe_sideload_otbn 0 3 0.00
chip_sw_keymgr_dpe_sideload_otbn 3600.236s 0.000us 0 3 0.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 295.710s 2835.300us 3 3 100.00
chip_sw_kmac_mode_kmac 362.300s 3280.441us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 370.430s 2921.382us 3 3 100.00
chip_sw_kmac_app_keymgr_dpe 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2763.080s 10715.968us 3 3 100.00
chip_sw_kmac_app_lc 14 15 93.33
chip_sw_lc_ctrl_transition 2815.330s 31702.016us 14 15 93.33
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 662.610s 10161.097us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 2602.810s 10554.718us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 333.800s 3230.734us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 695.050s 4753.411us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1670.280s 11550.116us 5 5 100.00
chip_tap_straps_rma 735.760s 5721.867us 5 5 100.00
chip_tap_straps_prod 2402.030s 15285.698us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 318.460s 2547.565us 3 3 100.00
chip_sw_lc_ctrl_init 14 15 93.33
chip_sw_lc_ctrl_transition 2815.330s 31702.016us 14 15 93.33
chip_sw_lc_ctrl_transitions 14 15 93.33
chip_sw_lc_ctrl_transition 2815.330s 31702.016us 14 15 93.33
chip_sw_lc_ctrl_kmac_req 14 15 93.33
chip_sw_lc_ctrl_transition 2815.330s 31702.016us 14 15 93.33
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_prod 2731.320s 12007.939us 3 3 100.00
chip_sw_lc_ctrl_broadcast 71 81 87.65
chip_sw_rram_rma_unlocked 905.530s 10010.120us 0 3 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 440.990s 3475.416us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 906.520s 6204.301us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1067.120s 6942.864us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1006.080s 6831.156us 0 3 0.00
chip_sw_lc_ctrl_transition 2815.330s 31702.016us 14 15 93.33
chip_sw_rram_ctrl_lc_rw_en 627.450s 4536.734us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2763.080s 10715.968us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1174.350s 17084.650us 3 3 100.00
chip_sw_sram_ctrl_execution_main 1066.220s 8432.667us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 2690.940s 28550.023us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 698.960s 4319.977us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 723.410s 4614.311us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 676.290s 4500.299us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 636.480s 4822.256us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 639.420s 3998.467us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 696.630s 4936.357us 3 3 100.00
chip_tap_straps_dev 1670.280s 11550.116us 5 5 100.00
chip_tap_straps_rma 735.760s 5721.867us 5 5 100.00
chip_tap_straps_prod 2402.030s 15285.698us 5 5 100.00
chip_rv_dm_lc_disabled 335.120s 6212.598us 0 3 0.00
chip_lc_scrap 5 6 83.33
chip_sw_lc_ctrl_rma_to_scrap 502.140s 5081.680us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 523.350s 7348.323us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 603.640s 10027.644us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 629.230s 9642.183us 2 3 66.67
chip_lc_test_locked 0 6 0.00
chip_sw_lc_walkthrough_testunlocks 3600.287s 0.000us 0 3 0.00
chip_rv_dm_lc_disabled 335.120s 6212.598us 0 3 0.00
chip_sw_lc_walkthrough 3 15 20.00
chip_sw_lc_walkthrough_dev 2851.020s 21165.004us 0 3 0.00
chip_sw_lc_walkthrough_prod 3086.470s 21773.951us 0 3 0.00
chip_sw_lc_walkthrough_prodend 2030.190s 19603.080us 3 3 100.00
chip_sw_lc_walkthrough_rma 1956.400s 15667.595us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 3600.287s 0.000us 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 9 9 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 482.210s 6494.032us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 518.070s 6329.471us 3 3 100.00
rom_volatile_raw_unlock 482.660s 5580.219us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 6141.280s 17412.776us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6410.140s 20090.482us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1045.520s 6004.582us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1045.520s 6004.582us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 1045.520s 6004.582us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 478.360s 3138.154us 3 3 100.00
chip_otp_ctrl_init 14 15 93.33
chip_sw_lc_ctrl_transition 2815.330s 31702.016us 14 15 93.33
chip_sw_otp_ctrl_keys 9 12 75.00
chip_sw_otbn_mem_scramble 478.360s 3138.154us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2763.080s 10715.968us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 718.800s 4253.675us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.181s 0.000us 0 3 0.00
chip_sw_otp_ctrl_entropy 9 12 75.00
chip_sw_otbn_mem_scramble 478.360s 3138.154us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2763.080s 10715.968us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 718.800s 4253.675us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.181s 0.000us 0 3 0.00
chip_sw_otp_ctrl_program 14 15 93.33
chip_sw_lc_ctrl_transition 2815.330s 31702.016us 14 15 93.33
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 715.000s 6234.013us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 318.460s 2547.565us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 23 27 85.19
chip_sw_otp_ctrl_lc_signals_test_unlocked0 440.990s 3475.416us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 906.520s 6204.301us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1067.120s 6942.864us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1006.080s 6831.156us 0 3 0.00
chip_sw_lc_ctrl_transition 2815.330s 31702.016us 14 15 93.33
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1739.790s 7442.802us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 498.730s 7165.584us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 286.640s 2926.676us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 280.050s 2399.128us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 797.270s 8010.914us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 508.800s 4635.894us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1643.720s 22091.670us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 6 6 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1850.460s 12624.148us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1031.970s 8324.562us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 468.650s 3691.944us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 599.520s 3635.495us 3 3 100.00
chip_sw_pwrmgr_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 498.730s 7165.584us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 362.720s 3424.508us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 905.820s 9973.228us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 556.600s 6398.596us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 320.140s 3318.911us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 902.580s 7786.038us 0 3 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1126.460s 6986.586us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 2312.520s 9357.756us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3280.580s 27835.178us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 333.610s 3031.140us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 93 100 93.00
chip_sw_all_escalation_resets 810.360s 4940.246us 93 100 93.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1174.350s 17084.650us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1174.350s 17084.650us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 9 12 75.00
chip_sw_pwrmgr_all_reset_reqs 2312.520s 9357.756us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 902.580s 7786.038us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 599.520s 3635.495us 3 3 100.00
chip_sw_pwrmgr_smoketest 520.250s 5908.316us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 507.840s 4251.503us 3 3 100.00
chip_sw_rstmgr_cpu_info 3 3 100.00
chip_sw_rstmgr_cpu_info 644.320s 4759.925us 3 3 100.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 438.540s 3357.295us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 2239.400s 12497.006us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 266.910s 3014.104us 3 3 100.00
chip_sw_rstmgr_escalation_reset 93 100 93.00
chip_sw_all_escalation_resets 810.360s 4940.246us 93 100 93.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1898.680s 7393.172us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 802.630s 4734.575us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 847.270s 4390.523us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 309.330s 3249.608us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 0 3 0.00
chip_sw_rv_core_ibex_icache_invalidate 3600.181s 0.000us 0 3 0.00
chip_sw_rv_core_ibex_fault_dump 3 3 100.00
chip_sw_rstmgr_cpu_info 644.320s 4759.925us 3 3 100.00
chip_sw_rv_core_ibex_double_fault 3 3 100.00
chip_sw_rstmgr_cpu_info 644.320s 4759.925us 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 233.310s 2858.765us 3 3 100.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 2436.950s 21508.742us 3 3 100.00
chip_jtag_mem_access 1 3 33.33
chip_jtag_mem_access 1906.070s 22575.981us 1 3 33.33
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 507.840s 4251.503us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 374.090s 3367.865us 0 3 0.00
chip_rv_dm_access_after_wakeup 0 3 0.00
chip_sw_rv_dm_access_after_wakeup 282.180s 3158.913us 0 3 0.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 735.760s 5721.867us 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
chip_rv_dm_lc_disabled 335.120s 6212.598us 0 3 0.00
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 896.810s 4737.923us 3 3 100.00
chip_plic_all_irqs_10 560.060s 3489.110us 3 3 100.00
chip_plic_all_irqs_20 670.230s 3624.670us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 316.190s 2552.786us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 322.440s 2854.411us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 5871.710s 15310.984us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 650.340s 5366.116us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 394.590s 3763.299us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 432.530s 2774.543us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 328.650s 3121.510us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 718.800s 4253.675us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 691.170s 4743.450us 3 3 100.00
chip_sw_sleep_sram_ret_contents 0 6 0.00
chip_sw_sleep_sram_ret_contents_no_scramble 266.090s 2964.058us 0 3 0.00
chip_sw_sleep_sram_ret_contents_scramble 323.130s 3263.790us 0 3 0.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 1066.220s 8432.667us 3 3 100.00
chip_sw_sram_lc_escalation 99 106 93.40
chip_sw_all_escalation_resets 810.360s 4940.246us 93 100 93.00
chip_sw_data_integrity_escalation 757.630s 5001.624us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1126.460s 6986.586us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1936.170s 23306.642us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 335.790s 3088.881us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 419.060s 3913.444us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 590.840s 4561.157us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 1936.170s 23306.642us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 1936.170s 23306.642us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 5128.510s 20266.322us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 5128.510s 20266.322us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 466.560s 5405.833us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.185s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 230.870s 3152.059us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 221.740s 2880.941us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 532.710s 3836.990us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 539.260s 3908.494us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1646.810s 7741.279us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 10127.700s 31114.178us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 3518.510s 11512.470us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 342.740s 3059.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 374.020s 2859.518us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 2 3 66.67
chip_sw_rv_core_ibex_lockstep_glitch 163.070s 2531.599us 2 3 66.67
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 0 1 0.00
chip_sw_coremark 18000.178s 0.000us 0 1 0.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 2080.970s 6142.457us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 141.600s 1991.061us 0 1 0.00
rom_e2e_jtag_debug_dev 145.800s 2209.803us 0 1 0.00
rom_e2e_jtag_debug_rma 126.820s 2193.790us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 133.770s 1848.949us 0 1 0.00
rom_e2e_jtag_inject_dev 146.800s 1671.500us 0 1 0.00
rom_e2e_jtag_inject_rma 515.060s 3810.415us 1 1 100.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 191.729s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 480.070s 3169.558us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 697.410s 2945.829us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1523.040s 5070.584us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 2179.720s 9870.375us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 429.270s 2340.969us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 464.480s 3478.270us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 546.790s 5666.757us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 574.200s 4685.243us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 2312.520s 9357.756us 3 3 100.00
chip_sw_rom_ctrl_digests 3 3 100.00
chip_sw_kmac_app_rom 662.610s 10161.097us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 141.600s 1991.061us 0 1 0.00
rom_e2e_jtag_debug_dev 145.800s 2209.803us 0 1 0.00
rom_e2e_jtag_debug_rma 126.820s 2193.790us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 2 3 66.67
chip_sw_rv_dm_access_after_escalation_reset 675.000s 4828.531us 2 3 66.67
chip_sw_plic_alerts 93 100 93.00
chip_sw_all_escalation_resets 810.360s 4940.246us 93 100 93.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 7200.257s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 7200.257s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 0 3 0.00
chip_sw_spi_device_pinmux_sleep_retention 339.420s 3351.381us 0 3 0.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 665.020s 3948.326us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 6056.160s 19113.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 22 13.64
chip_sw_rstmgr_rst_cnsty_escalation 73.150s 10.120us 0 3 0.00
chip_sw_otp_ctrl_rot_auth_config 151.460s 1764.350us 0 1 0.00
chip_sw_otp_ctrl_descrambling 370.100s 3461.244us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 362.050s 2858.423us 0 3 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 16.051s 0.000us 0 3 0.00
ate_bootstrap_flash_erase 1440.870s 10010.280us 0 3 0.00
ate_bootstrap_one_frame 10800.247s 0.000us 0 3 0.00
ate_bootstrap_disjoint 10800.214s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 90 test runs
chip_sw_alert_handler_lpg_sleep_mode_alerts 112515826032226147163450053021739822491814891120859617031506913813246741697523 373
UVM_INFO @ 2754.492829 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 54404517887707043970364186452454495268136364339249349183172016141958120003536 373
UVM_INFO @ 2565.860460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101675726492790393567452439720090461741732273608769952968702123693278528636814 373
UVM_INFO @ 2639.611204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 98395170298686657942042111654761939549325541305822719512922866564929751222107 373
UVM_INFO @ 3003.225575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85908389765755721772045689143118757737441465878982988310867450387155558657454 373
UVM_INFO @ 2884.663688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33333883975543644901317778545858560294777544308529753040767724447452285930051 373
UVM_INFO @ 2023.147032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94500355905845129797500389920632661183237612982010723730068196066916212622206 373
UVM_INFO @ 2586.894985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 17171378785637216240557469745531163080219615845116986856024263476749672225055 373
UVM_INFO @ 3371.906124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85322600689133198925943289952313105705595070305207061233625982413792836988044 373
UVM_INFO @ 2730.510203 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 113231337146555305417528179703587805534932567004491851738001928216280626449711 373
UVM_INFO @ 2358.276559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97655221909317821823180352125685824095873670048977389388932903940386005935231 373
UVM_INFO @ 2843.511440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108640534761051684216832960901893370764423561077221432111436486738119730077318 373
UVM_INFO @ 2713.248144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7115630690540010948785184198013361805081875430052736304334758513088843939271 373
UVM_INFO @ 2492.738664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38214318212587493241679634477093828250481556279085730449052671301740398106394 373
UVM_INFO @ 2869.324825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4726267415370123784889315137269988087027560224355475204122974686558902911285 373
UVM_INFO @ 2498.742619 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39871065958530393808257400498779949090422210484067344595700317068815105402643 373
UVM_INFO @ 2837.047480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 83589092312848160410022528462915202745388707525007442626938216737432336461817 373
UVM_INFO @ 3066.442872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27671279088387011937956658015616588025035372095201870402330067252551544441059 373
UVM_INFO @ 2456.249496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22264920890447644026852860802058566425737434261616731338435377038371774847618 373
UVM_INFO @ 2705.374034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49894412969214057823064362346870152593281484150939353801485551853188915005340 373
UVM_INFO @ 2584.577995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91143760279666761794237296413685376078176358566496738561171122897176907244113 373
UVM_INFO @ 2298.544600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70804749370137828784503652563236390450472639434102068661114632116042492743868 373
UVM_INFO @ 2786.579880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89032895726775088302605004945336949608498078918257184659660594335902449354238 373
UVM_INFO @ 2537.737072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106235119464399771793473191942031570981693181439577884103832553701656742180031 373
UVM_INFO @ 2924.042492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 64018312766555556822080761736848466471340316622875666858923177042504699792716 373
UVM_INFO @ 2454.271441 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19378023995559247134550406430192776531493923227188631733915814397945436202727 373
UVM_INFO @ 2607.022808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92731559774600364928448715236776515014949776111481080406420343547017026376954 373
UVM_INFO @ 2890.845697 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65465400596277855301778421854471635250214322226044015818330059049033255640867 373
UVM_INFO @ 2753.522993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40171130926413628556078689886662900196934235116415961815961255962887048943557 373
UVM_INFO @ 3043.773397 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14082814406150965051837868852541114101826928977398182975253062746921427013793 373
UVM_INFO @ 2699.547736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78214153958257946239729843847701405460176733379622931013234291893007471053789 373
UVM_INFO @ 2295.800970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79273142461881993036212588525732875169289943367620195703328394672340258791782 373
UVM_INFO @ 2108.813400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93190563516165248089589295409080820476520041682923615991353536026484079445095 373
UVM_INFO @ 3348.126198 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44406547088627502589808795571112898313805281286485121411091089910240631316334 373
UVM_INFO @ 2641.326888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79111329398412801563539548947579526158295433998160735924629940160432340476071 373
UVM_INFO @ 2681.854663 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4246743452068159637749743484424436520559218856599544611690630073161941769914 373
UVM_INFO @ 2687.958296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21501080697597409263289496631750579172368370947678690070620485007025318993311 373
UVM_INFO @ 2818.326550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102633042411381171147301028072029003901708009511305450475696259110737831214788 373
UVM_INFO @ 2960.176805 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23846195968004257814015778014442982868398926443716848511517278505906602837396 373
UVM_INFO @ 2524.626760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59911261655767748823100238657832154101035817557662761414312923208802141186029 373
UVM_INFO @ 2592.872926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 56502551660008877509502413419372287463055249753033690681444523817387811051837 373
UVM_INFO @ 2245.690210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48047589760509726802282403434011142559555357527946780196726933205995490539272 373
UVM_INFO @ 2646.364591 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99758922588242921773857966879008053490831729582271241493155596646037829734507 373
UVM_INFO @ 2542.616295 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77776633839068648681527784883439966164959796158374372888216429732157369184805 373
UVM_INFO @ 3274.797195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 80356632123424399488696733700881556541965443868746511101826678574986271792782 373
UVM_INFO @ 2829.328352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30682346857605644931638016473020050344737845867326125429504138562450789284616 373
UVM_INFO @ 2915.427637 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96210738828588518693856454314578449541033048821205345098934695134911792064629 373
UVM_INFO @ 1944.831990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8399606767105990748950559366307821872297152753540741499277285066276057586737 373
UVM_INFO @ 2727.964720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 10015321690271275035894448756337772342678579316785154636768608528963443243246 373
UVM_INFO @ 2546.432292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16256006632665544877470141676583197218974024184421408773236800137388800083977 373
UVM_INFO @ 2303.199536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112301490070042130082267838368031869994837941994995841680694920962571638562125 373
UVM_INFO @ 3083.343924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46831932656222054210936753490598567665913990620084875676361156661709068382360 373
UVM_INFO @ 2657.074165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58881732526698439808178947577961320867900253261487063671085901093390153281072 373
UVM_INFO @ 2282.977462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 64395452124503855919160764519779290452579566427948282023647063710754967671840 373
UVM_INFO @ 2843.115270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4033305363426771759958949149173779539955618702605285429004446232859819240478 373
UVM_INFO @ 2599.314694 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73836642040181596169234811483259251342106257700943417819716805229375163306020 373
UVM_INFO @ 2821.882015 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6788267631217757542092491970692331661211213953189084665537214940998738961784 373
UVM_INFO @ 2517.193455 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 43104745765975446816915795371584791920781613816152497756195847459368075866726 373
UVM_INFO @ 2645.532896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41141244187586240220075846383058858324079581894573399799709695008673014726774 373
UVM_INFO @ 2561.176582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86990988790440974669643554915455849879231293003532525691557485740766349366261 373
UVM_INFO @ 2070.678260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106319326904851080513382085084109222613720566899787645448814421202005294536975 373
UVM_INFO @ 2640.446394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34616980652333972731290785544736600233051093275154202352275138600272177541837 373
UVM_INFO @ 2966.778670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 111127705567701262699782639634351724379114686626162617682273674741126964407748 373
UVM_INFO @ 2932.172196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61589407612428563752512825406478251523985979995056413001055332121469949889214 373
UVM_INFO @ 2498.052180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65641643968345936246366606173970913193437675239896005436390539619471989896791 373
UVM_INFO @ 2706.584940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 76989612751827191839344027565325352569015846908443853057595782799677568397191 373
UVM_INFO @ 3033.617576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41996862059622130306150319136638913345499578371777641868051650765898732706325 373
UVM_INFO @ 3111.377026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47621916279113142866568121046708081903182515715813128654600829116814127184876 373
UVM_INFO @ 2991.082155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 64846563518731720640580631920858521614057925874995294263699383267105537874882 373
UVM_INFO @ 2871.496456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 2738542382319046333578566351311915746707581196125800555272540297806127615356 373
UVM_INFO @ 2630.596988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94174597326543063984651631552372982191144719903916234199862416476662502633244 373
UVM_INFO @ 2945.701873 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47655520777345775237731101605605395854743609544817362876598681139522905606372 373
UVM_INFO @ 2349.533016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32826525816291843411903282344306236000443524599004948099348072720424006780301 373
UVM_INFO @ 2981.107921 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28707525202358275646284763805226022442812747789763988767625552142377462157995 373
UVM_INFO @ 2652.958552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 110484709561997888727152988634090883633842221306417530048865155188261152137902 373
UVM_INFO @ 2260.813432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32867861845263176056964894051077800922976386321899695004516983551494796254014 373
UVM_INFO @ 3127.657030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 87468597507318768511471210936312436529412536769278125995416430263134780570617 373
UVM_INFO @ 2910.321496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34490410315984272083933980396048625311248565605975956812265010002961067524237 373
UVM_INFO @ 2488.248510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65725345985390557657082179192806867227499891652259237050737217709654565846399 373
UVM_INFO @ 2659.695283 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69397245117043273649008229046445214721901841250430701179076067004597603342377 373
UVM_INFO @ 2949.901410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 1957049950029421814492400794745433260634494569228483895689032825978704327194 373
UVM_INFO @ 2182.225800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97828487568177337116167094631253064640264642284330197200170486795672281183275 373
UVM_INFO @ 2865.908690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42809954038078728378602589769133596057404349502639421281298896481233200217954 373
UVM_INFO @ 2548.539199 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62445822892082377264195058147998611363912278475984423585452951482917820484503 373
UVM_INFO @ 2327.464421 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 72400737914781684481814907392528012007981611937225652364120876179736405896553 373
UVM_INFO @ 2937.288905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 60222532040300613925665742308428582398112404973794890216444443872385559121003 373
UVM_INFO @ 2609.927440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 80160771908353408792074798308749134959313420576648579875066800371117472907840 373
UVM_INFO @ 2685.129816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 83734982477440246547144611819546320023062694831847629415115444778235214728232 373
UVM_INFO @ 2410.110696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70444428852274664864897410329736145626872969108493609689993803437839613449566 373
UVM_INFO @ 2760.289971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79353611957387019822010765435112840752423042366721523657337765506850890312662 373
UVM_INFO @ 2417.191320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error 41 test runs
chip_sw_sleep_pin_retention 56508339161022505085846715023845737990436670989478934414869097584888952282110 379
UVM_INFO @ 2834.442314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 38557083391297717977890912009018051582932826486298616569190060471515370212185 374
UVM_INFO @ 2631.770104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 39406029503905805394918809662007370198593117526589547834691087133598102676110 392
UVM_INFO @ 7170.910290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 100631850276537883410098795247636734891358959040386686270469483707250867714926 377
UVM_INFO @ 3291.170832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 85581474145580764452492457936445389625502845283433931441565781544215330364272 388
UVM_INFO @ 4672.915680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 33763079577867113652517089905287187909699542200278589845337234336605234866347 391
UVM_INFO @ 6158.668320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 93926888240628776577889729388166605463521212693081091228448505885171019233510 377
UVM_INFO @ 2517.290886 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 52412717144982089331477844279014508387851488886651525066383104963379224266926 381
UVM_INFO @ 3263.789688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 19758066470680914312098789740941696010593328817066212382526727163732193787367 372
UVM_INFO @ 3018.777668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 58579696835169791817420535386188099066964224119452692788955474898233471185997 407
UVM_INFO @ 4174.692422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 32948066457626235185671355861728055821550130860485003202341996393216687495233 374
UVM_INFO @ 2399.127808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 108436643155359294909491011310310317083724610029079189011963016291937656330705 372
UVM_INFO @ 2858.423088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 46674065370687038714427336383648359918602379113197228931596765552613958419554 373
UVM_INFO @ 2926.675896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 95968147646078456926359837570692956950023931294039930829345752752887966014336 382
UVM_INFO @ 2770.699214 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 6283475908681896567987919632168772962986566889833697641323819873412079390124 379
UVM_INFO @ 3128.149120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 49102571255930158783035251366891017062135922651123976141720763598658484218690 374
UVM_INFO @ 2994.045584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 60542725330292222212599573214705030621341650309705596241374823968674206580637 392
UVM_INFO @ 7786.038372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 106386392565483149509465010134060774050956612796611750557077823449612891201799 377
UVM_INFO @ 3691.943896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 5268384534512417808336491818175958307333270876091244364473500217560286066976 388
UVM_INFO @ 4635.893982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 8356244408516221490199428079337405575666003507475404180118874693098355846814 377
UVM_INFO @ 2968.155816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 35136609823343457845953438685832856279069184874040118604122993636059700304956 381
UVM_INFO @ 2788.714908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 20041400179531528615033094972720863732430988366465605624358222266732131742257 372
UVM_INFO @ 3262.424728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 5009468662225381816311347363326594551478337144188766065988194414366623269418 407
UVM_INFO @ 4329.938334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 90032056142393450875197585713384557791859581018930557271964326963422583036076 374
UVM_INFO @ 3267.572768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 84642410785579190940243065202807614457568691984918619940470559928359817038653 372
UVM_INFO @ 2994.804788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 26568128129260685526871539778577299592282892718353389113523125004589647462894 373
UVM_INFO @ 2699.334120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 108592962855289321395231243877693549913141559168601900887927913104982336407026 390
UVM_INFO @ 3029.332328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 5326036097989101278690903941380394126639836169208554391838872185099852152768 379
UVM_INFO @ 3225.863752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 82047224400763153848948486907593906348057197280683822392509582105481470330159 374
UVM_INFO @ 3351.380520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 47390658198417845453284838731122607983196772430549118499748786019102269568511 392
UVM_INFO @ 6545.094220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 47652782523335024381043970716351211051168262191106029071949644065718495284182 377
UVM_INFO @ 2865.661648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 94523764850426786396208130750782320087444014288446019685776733960536588398228 388
UVM_INFO @ 4487.450067 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 82880706647015403258577965781089045469774772099133346957725313376153597599872 377
UVM_INFO @ 2964.057676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 82918519440661788892424636867949647556850966401742397733619034485354425407429 381
UVM_INFO @ 2455.915496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 69691775080692075754639937460865655992039388727603606864474472371357834665566 372
UVM_INFO @ 2467.604072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 2011538563439010735909756036658652377798953802995171441529695118513842435790 407
UVM_INFO @ 4697.689696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 93177505461361224826677890909782497914205332124948324000618240978963034269584 374
UVM_INFO @ 2724.013028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 33571097057246764554149067886690470982321501841965528137887573239637999874030 372
UVM_INFO @ 2561.491212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 65838781559467551050307580813681578464339824191383391287470302038528293837771 373
UVM_INFO @ 2751.262796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 91225947755334321448878856456780953866407711223934049457236384132835000374510 390
UVM_INFO @ 2645.768196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 17241708743929878100408745070122573322790415540091334026980833844054541823634 387
UVM_INFO @ 3542.290008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 38 test runs
chip_csr_aliasing 17616070919958754553234180752065387148170463336597869919344469961107640216937 None
chip_sw_uart_tx_rx_bootstrap 77289475719565013561079461803096532511212437779048867862470496192420260765806 None
chip_sw_exit_test_unlocked_bootstrap 30988714150306652688770194769007561264950044129618264428605541987085005896626 None
chip_sw_lc_walkthrough_testunlocks 92481729711321082977964086510021270672419002727433458647068512490149651492881 None
chip_sw_rv_timer_systick_test 60072735060080438183939817253958741727122524423118968364519925349840846862488 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 34556869794364420158604607488294395998756216627103946155617783160629285900700 None
chip_sw_keymgr_dpe_sideload_otbn 44726105496609117784067252746554812969826896595599654975866357294686244149767 None
chip_sw_coremark 19594692388141601928663942215132932541558427329886208235905060155418234483472 None
chip_sw_rv_core_ibex_icache_invalidate 29914511389402579908982876834543294789578413899808663524862673853749361040465 None
ate_bootstrap_one_frame 99855706287287562968455282874177044488851634347686354152090437170583497794856 None
ate_bootstrap_disjoint 1141277032644006547583636549522158354014472593129305257612558845555344596894 None
chip_sw_uart_tx_rx_bootstrap 53357860449721496904975223628759322490239246724726672786652519687965346706935 None
chip_sw_exit_test_unlocked_bootstrap 14146173198801061972374669508905008101439779516217927572595368819002333037449 None
chip_sw_lc_walkthrough_testunlocks 56087149690471601625907310214989624512723179676803088370085317551122166207669 None
chip_sw_rv_timer_systick_test 161614306532625393585420133291168318787560627118217181610481060288028966517 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 44470221598342226103402556514376245864333311277202523002685448607168854012560 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 24827221230177536084407176285143704338213210567011399256644069972211643748854 None
chip_sw_keymgr_dpe_sideload_otbn 7690521682078494476455237253417744743989817642088701955698203319087830812877 None
chip_tl_errors 37796153982780898453463312250931575421414314833281296410961675134887080948771 None
chip_sw_rv_core_ibex_icache_invalidate 48384799646587007820834976807966475984474332508124129561519816989884945187330 None
ate_bootstrap_one_frame 55722538913767923316036752843703834534324492377670254890926851478320976680175 None
ate_bootstrap_disjoint 90990014508606445025140942863564314174067173027240067744741847096654414773259 None
chip_sw_uart_tx_rx_bootstrap 544625410912483405820599718757825515329502993451710799766563781636691866282 None
chip_sw_exit_test_unlocked_bootstrap 115269905587315977077655188617390245166678445217261042682147603321247267942204 None
chip_sw_lc_walkthrough_testunlocks 41948385719243585557250339491331504336760308303553009974035302064697131667055 None
chip_sw_rv_timer_systick_test 50360411362899060128094682521233113137684766370253597609145175079513974372184 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 84848775720974510321509374044556645203234132018966681598680071462828958920282 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 88193338117632841354083664894416165533820145612703474510418391200296383398425 None
chip_sw_keymgr_dpe_sideload_otbn 58123149081826302915441781463179452548976042233979302730811564989353571183544 None
chip_sw_rv_core_ibex_icache_invalidate 67328517775810074791929149357110698076125045184085679563900049662563306296539 None
ate_bootstrap_one_frame 45972555937543042317109162262490020698638858072005416579462167805336426639677 None
ate_bootstrap_disjoint 111209891821612846613075363873833789537531609829903072376003878469057843421994 None
chip_tl_errors 51908890624394807346388419390994393622349234436877969973747560874920727052394 None
chip_tl_errors 49591037201125565428879841236877932671681165805846979346667619329505346953030 None
chip_tl_errors 83196188832371222215083650167971438596232764137324251634534708868073070274305 None
chip_tl_errors 13132003940195671043626965258717348168369415824992323948401792002164323389503 None
chip_tl_errors 81368552075013756709276953489092355170200017701956188736934757204449544183196 None
chip_tl_errors 61757936103211052316429540300501015492234787855606119716470658240996107479646 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 9 test runs
chip_sw_lc_walkthrough_dev 40268970377019537163886986012888318063247096609879480939051184015340325622790 433
UVM_INFO @ 21165.003728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 61560964490237637236145882534130126785395500212986616300745117066985308121173 433
UVM_INFO @ 21773.951092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 35187855255041718168457766677584931394283899999148240963576750586141627819297 405
UVM_INFO @ 14347.215674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 106175275143557672104322448942196233272835151522621842320465102660824238890088 433
UVM_INFO @ 15296.837738 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 97630413455787041889752904872235721477247611232638739838433532776236833355995 433
UVM_INFO @ 16930.864964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 41113430260005720712722320647471513305945060940882043715481492068601081845880 405
UVM_INFO @ 15667.595256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 105905861236222129274153321000399698566133854112845013663311050716147565348775 433
UVM_INFO @ 19397.197824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 104579839767500129122439616456859651255641426589939794436969746355780690044936 433
UVM_INFO @ 14605.757856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 110353679582203355199498964475323043175004148180468083922548038778071693193294 405
UVM_INFO @ 12367.381865 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 7 test runs
chip_sw_alert_handler_reverse_ping_in_deep_sleep 11668514215077649828146464020598641579860027507507096187411832156768626483554 372
UVM_INFO @ 16397.603078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 71490679359110791912766431050852243816890637319226507388911105848785042390936 373
UVM_INFO @ 2983.113480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 5534786635797680397808070620280075347858231489122979393114231350361452026229 443
UVM_INFO @ 3222.031160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 26870220691005902684035831719282345732256061556271844714035924669318425736836 373
UVM_INFO @ 2789.431476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 110074105898295465459621733934821203515149001862445842641954850362158944992200 478
UVM_INFO @ 2353.644324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 81717834750990273512700132149372412364586195445058012648943679784200390096429 373
UVM_INFO @ 2472.781608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 41040263060979676318447290235060273722249685992101202357085781187882823658951 465
UVM_INFO @ 3276.513418 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 6 test runs
chip_sw_otp_ctrl_rot_auth_config 49947045209700934452933649653192684209573455869431803006053396832734859126018 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 49021254212433130469440525108051719365743906614982991660027000865645596871762 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 78603701894310452563257558664203412949759368661324755981167659007497440300539 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 5636923001925300206986139492276607026472214124542906959635318245254158970182 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 6729470814514541541142621367779700530428911080350752284490105629450792971185 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 19073927389819042353223013046858365312856062709991727394504345050666567947766 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 6 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 93322364882894631146751197169074324860227247470121198219015906774853099624475 None
---- STDERR ----
Another command (pid=4160847) is running. Waiting for it to complete on the server (server_pid=196609)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 8622965798203668492364945369129680028020897091312147403001834608347717402445 None
---- STDERR ----
Another command (pid=196593) is running. Waiting for it to complete on the server (server_pid=196609)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 32027542174158606175538019770657014478181359903755941419521828864537276001609 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 68032947625405118962600849835743419756127218819848405874785983876774849336159 None
Another command (pid=267667) is running. Waiting for it to complete on the server (server_pid=196609)...
Another command (pid=280745) is running. Waiting for it to complete on the server (server_pid=196609)...
Another command (pid=284700) is running. Waiting for it to complete on the server (server_pid=196609)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 70371877086312104058461563844653373844799384169160933121014597572248403683153 None
---- STDERR ----
Another command (pid=1707909) is running. Waiting for it to complete on the server (server_pid=196609)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 6672248820166115720432897155620161476673404318929512541038800030434577072791 None
Another command (pid=251549) is running. Waiting for it to complete on the server (server_pid=196609)...
Another command (pid=232354) is running. Waiting for it to complete on the server (server_pid=196609)...
Another command (pid=274074) is running. Waiting for it to complete on the server (server_pid=196609)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 5 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 22195046322749096977604857638256126922078672145047656995200249060734918455180 377
UVM_ERROR @ 3318.910808 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3318.910808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 5480865549370756165734295223128899746120179153486943952925051827860897589680 377
UVM_ERROR @ 3191.034344 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3191.034344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 93644788400881306645605859077367784650057658492828240473669197047392617417750 404
UVM_ERROR @ 9973.227640 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 9973.227640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 34332335487675587303548068953986645623360985300034296601607317167619058160252 377
UVM_ERROR @ 2489.086008 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2489.086008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 27836205162754879709882260487428037777850092641616375838690769162782312139743 392
UVM_ERROR @ 8552.996415 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 8552.996415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 3 test runs
chip_sw_rstmgr_rst_cnsty_escalation 109108301654212211456380674006513511690490239933824021268039757324849812131682 365
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 32352788495312202873292328772995716619734520618066038995210989758601816529462 365
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 73347923564761658299250034916849678506804673614139677233874666509659107705779 365
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred! 3 test runs
chip_sw_rram_rma_unlocked 24698302132120639767856047347458963686826600716513980987548826824311556585894 337
UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 35559565817424892853124680594374672798230523142101232370266446700207146283781 337
UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 16073603547692505370446276204191471582962809441799297097309950840697234512831 337
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 3 test runs
chip_sw_otp_ctrl_lc_signals_rma 94316974169741713836372186393098493913147158349758943072182771626105189080101 404
UVM_INFO @ 6604.188740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 12451413278755293189535546789799243198601051590958627929606252385191282761449 404
UVM_INFO @ 6080.426955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 113885542320840023918412177776625621899201203648575618595672664529182462394068 404
UVM_INFO @ 6831.155639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 3 test runs
chip_sw_hmac_multistream 71082859412634036954560536239876844935297225795081255010333221911795506789907 401
UVM_INFO @ 12010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 87609376182006608831104177147781100404826368483001874138956263182117032068775 459
UVM_INFO @ 12010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 87846309527428974470708614104591502462019778800995395955372115504677969752270 450
UVM_INFO @ 12010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. 3 test runs
chip_sw_clkmgr_reset_frequency 101958159513324328414929241586818417398567460603599183228392993901826255154115 400
UVM_INFO @ 7737.890640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 12862633514363122454347467785667765637956104869592070805648839216965503562079 400
UVM_INFO @ 11285.141970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 112377316626816046777499055762828713467605777905808367816592960596962866733435 400
UVM_INFO @ 6534.479478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_clkmgr_jitter_frequency 13033280324623627384901142729384041159147990235070499627047886550806498051105 407
UVM_INFO @ 3169.558361 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 3281546906999308872201425835904059584341348457685031770706857345010683969958 407
UVM_INFO @ 3784.572727 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 24198874065504306242822597573368526368550821210266523000019091367290251741584 407
UVM_INFO @ 3350.118318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [*] vs * [*]) RV_DM sbaddress* read back check failed, got *, expected * 3 test runs
chip_rv_dm_lc_disabled 92298947307993007971757460668677616522229577649327158570554856232449344562313 328
UVM_INFO @ 6212.598125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 24639628224733072954017675665641727202119203752336449147827103928874143459316 292
UVM_INFO @ 1748.995780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 45998777188967741554872863468894728519067499753588609734263023537964663361602 292
UVM_INFO @ 2309.154348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 3 test runs
chip_sw_ast_clk_rst_inputs 113871142174088615940225663745660513385158185146980234482157552082407091367599 391
UVM_INFO @ 14479.097988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 65316036529956355896502372864512918724823030045807587274559242035949719521985 391
UVM_INFO @ 13835.417507 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 110299169516925522475417543454030239472397797270947696151339207313181385969358 391
UVM_INFO @ 14311.767784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 3 test runs
ate_bootstrap_flash_erase 42229885866488990046229005973051325457089471486488765707535658746161606737701 339
UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 69742801082929938213607994942844164177729900905671634831364602373570900185313 339
UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 30055916118451668974336766854153126956543187199991356926837097248146153680927 339
UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [*] vs * [*]) 3 test runs
rom_e2e_jtag_debug_test_unlocked0 46926330995772584705124034058987948363231120253952219806943302558805167152787 359
UVM_INFO @ 1991.060500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_dev 40815395988582864414555557195730099107158240449561822358418827204065510135291 359
UVM_INFO @ 2209.803000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_rma 114305358905833630320676125135023244484694090092114281480482762175452204783306 359
UVM_INFO @ 2193.790000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 3 test runs
chip_sw_all_escalation_resets 94464538829847383829035346039384678348498837658461346742910417327602573376781 383
UVM_ERROR @ 2819.656936 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2819.656936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 45802857198628729301151297011799609168946235433791841162942849830465295099485 383
UVM_ERROR @ 2862.455556 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2862.455556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 33993272025101087215813651334562788956692569279684761265879624301347657613317 383
UVM_ERROR @ 2451.686336 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2451.686336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:614)] CHECK-fail: Unexpected mtval: expected *, got * 3 test runs
chip_sw_all_escalation_resets 19940865193471717220862967222714539660037888564522749337857099263880321669010 383
UVM_INFO @ 3005.260154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 75442691941219415136202910990053828436586482892252130619929742271493879478352 383
UVM_INFO @ 2574.839270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 24047457025397211524713818549665682731512397104458767788131920842193113296766 383
UVM_INFO @ 2385.550030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 2 test runs
chip_sw_spi_device_pass_through_collision 21381341897207094148273950079343912678325695268680283965796476624862465641364 391
UVM_INFO @ 3763.298622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 29037784204662357479171543228115021002783954459701693863853111372576485729413 391
UVM_INFO @ 3034.578187 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:385)] CHECK-fail: Expect alert *! 2 test runs
chip_sw_alert_test 100093231201821078568960311946928482260432683968395574135748267693115204343718 371
UVM_INFO @ 2628.468109 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_test 82247430461449798488756615737397915391402523369620401213867657013216731856107 371
UVM_INFO @ 2300.182240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts! 2 test runs
chip_jtag_mem_access 71627013480284882027345633173030447733639150582626854593683495745183887338559 5365
UVM_INFO @ 2627.130258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_jtag_mem_access 64586553082811159942793182124217826674454366668507144160941004918098519469433 5365
UVM_INFO @ 2816.178340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:715)] CHECK-fail: Alert handler NMI state not expected: 1 test run
chip_sw_otp_ctrl_escalation 55522255355567564086594974276181858294513301037585530953145123982043253772102 379
alert_enable:1
alert_raised:0
UVM_INFO @ 3478.270484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * straight after write. 1 test run
chip_sw_rv_dm_access_after_wakeup 82053301618458404525224806370700489306582949038901341532782520591612133740525 385
UVM_INFO @ 3158.912683 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 14956385985502463746104253063602701669489031593556238283537290564923166778157 387
UVM_ERROR @ 2922.994852 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 2922.994852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 8463325715706854309736757846883059416462774262516163598759344305532202486958 386
UVM_INFO @ 1955.770672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement 1 test run
rom_raw_unlock 76337228958745786488209236628264624783683624291013412664515423492277140266118 398
UVM_INFO @ 20201.934240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 21605842873594999771886306734899599998044597205777622358970943941693419908689 371
UVM_INFO @ 3037.323880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 1 test run
chip_sw_spi_device_pass_through_collision 9661921429927005588015275929849201887581284576788189947032907299587444593756 393
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 1 test run
chip_sw_lc_ctrl_rand_to_scrap 86772096993087599853063063778667010646981654466673604550835270763495574684905 375
UVM_INFO @ 8283.550435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_if.sv:154) [tb.dut.chip_if] Detected an X on MioPadIoc* (num=30) 1 test run
chip_padctrl_attributes 8532806343158764546532529923056255706083011939624684797036045705682799312651 386
UVM_INFO @ 1875.920153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly 1 test run
chip_same_csr_outstanding 39063707964025141677265024284700114958631077660710809141171894725478053014235 283
UVM_INFO @ 22505.539224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_transition 79616397509970222760294977632908706435641393749955052768175851720208674476848 369
UVM_INFO @ 25724.793446 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1072)] Unexpected fault 1 test run
chip_sw_all_escalation_resets 10133254589157519946612546909793129772593288158610902738785179722112734063583 375
UVM_INFO @ 2574.838000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---