Simulation Results: clkmgr

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.39 %
  • code
  • 98.87 %
  • assert
  • 96.47 %
  • func
  • 87.82 %
  • line
  • 99.29 %
  • branch
  • 99.06 %
  • cond
  • 96.02 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.48%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.330s 68.167us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.000s 18.325us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.130s 19.285us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.570s 150.083us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.130s 15.719us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.460s 279.028us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.130s 19.285us 5 5 100.00
clkmgr_csr_aliasing 1.130s 15.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.180s 22.551us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.790s 153.465us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.920s 222.906us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.070s 42.136us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.330s 68.167us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 13.910s 2480.289us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 11.990s 859.416us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 13.910s 2480.289us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 61.220s 9299.739us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.420s 121.934us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 7.790s 1391.163us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 7.790s 1391.163us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.000s 18.325us 1 1 100.00
clkmgr_csr_rw 1.130s 19.285us 5 5 100.00
clkmgr_csr_aliasing 1.130s 15.719us 1 1 100.00
clkmgr_same_csr_outstanding 2.630s 305.264us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.000s 18.325us 1 1 100.00
clkmgr_csr_rw 1.130s 19.285us 5 5 100.00
clkmgr_csr_aliasing 1.130s 15.719us 1 1 100.00
clkmgr_same_csr_outstanding 2.630s 305.264us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
clkmgr_sec_cm 8.630s 2414.932us 5 5 100.00
clkmgr_tl_intg_err 5.940s 853.107us 25 25 100.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 3.350s 917.657us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 3.350s 917.657us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 3.350s 917.657us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 3.350s 917.657us 20 20 100.00
shadow_reg_update_error_with_csr_rw 13 20 65.00
clkmgr_shadow_reg_errors_with_csr_rw 5.930s 665.319us 13 20 65.00
sec_cm_bus_integrity 25 25 100.00
clkmgr_tl_intg_err 5.940s 853.107us 25 25 100.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 13.910s 2480.289us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 11.990s 859.416us 10 10 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 3.350s 917.657us 20 20 100.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 2.640s 373.256us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 2.870s 466.648us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.520s 97.643us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 9 10 90.00
clkmgr_clk_handshake_intersig_mubi 1.340s 35.462us 9 10 90.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.530s 271.692us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.130s 19.285us 5 5 100.00
sec_cm_idle_ctr_redun 5 5 100.00
clkmgr_sec_cm 8.630s 2414.932us 5 5 100.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.130s 19.285us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.130s 19.285us 5 5 100.00
prim_count_check 5 5 100.00
clkmgr_sec_cm 8.630s 2414.932us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 8.990s 1153.136us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 66.360s 3952.093us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 6 test runs
clkmgr_shadow_reg_errors_with_csr_rw 50483204450773776638571786481700360521520771779785484676221863137473878784524 82
UVM_INFO @ 146393360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 72401216367092254372899410059155425314793274224120574461923843592155039195612 81
UVM_INFO @ 54539813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 38567844136309104410796319770350616610834766450455267268052075143130699734977 81
UVM_INFO @ 90775700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 66884510083806618217579749893061630175126820140605734757292530245667192808285 82
UVM_INFO @ 129763387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 110390772506024276749820984265419404092624493682453204337286934499288016629596 81
UVM_INFO @ 141249317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 11468602670302225843080399102819009703234238333413516311025796897477765213559 82
UVM_INFO @ 147547313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 71467559930633935799053996748769844635039331990661116593141525297365046039141 80
UVM_INFO @ 4003955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 22900806657771661257518699045574752474255473017673669315692054996071509908416 81
UVM_INFO @ 24366713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---