Simulation Results: csrng

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.01 %
  • code
  • 96.22 %
  • assert
  • 96.94 %
  • func
  • 91.87 %
  • block
  • 98.53 %
  • line
  • 99.58 %
  • branch
  • 96.40 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.92%
V2S
99.92%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 8.000s 56.018us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 21.139us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 3.000s 12.649us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 26.000s 651.717us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 54.947us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 62.213us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 3.000s 12.649us 5 5 100.00
csrng_csr_aliasing 2.000s 54.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
alerts 500 500 100.00
csrng_alert 101.000s 6872.300us 500 500 100.00
err 500 500 100.00
csrng_err 13.000s 23.202us 500 500 100.00
cmds 25 25 100.00
csrng_cmds 236.000s 13853.999us 25 25 100.00
life cycle 25 25 100.00
csrng_cmds 236.000s 13853.999us 25 25 100.00
stress_all 24 25 96.00
csrng_stress_all 1320.000s 87713.443us 24 25 96.00
intr_test 10 10 100.00
csrng_intr_test 3.000s 24.757us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 3.000s 54.749us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 25.000s 1881.385us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 25.000s 1881.385us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 2.000s 21.139us 1 1 100.00
csrng_csr_rw 3.000s 12.649us 5 5 100.00
csrng_csr_aliasing 2.000s 54.947us 1 1 100.00
csrng_same_csr_outstanding 5.000s 161.907us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 2.000s 21.139us 1 1 100.00
csrng_csr_rw 3.000s 12.649us 5 5 100.00
csrng_csr_aliasing 2.000s 54.947us 1 1 100.00
csrng_same_csr_outstanding 5.000s 161.907us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 8.000s 154.024us 5 5 100.00
csrng_tl_intg_err 26.000s 1867.872us 25 25 100.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 4.000s 164.227us 25 25 100.00
csrng_csr_rw 3.000s 12.649us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 101.000s 6872.300us 500 500 100.00
sec_cm_intersig_mubi 24 25 96.00
csrng_stress_all 1320.000s 87713.443us 24 25 96.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
csrng_sec_cm 8.000s 154.024us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
csrng_sec_cm 8.000s 154.024us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
csrng_sec_cm 8.000s 154.024us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
csrng_sec_cm 8.000s 154.024us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
csrng_sec_cm 8.000s 154.024us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 101.000s 6872.300us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
sec_cm_constants_lc_gated 24 25 96.00
csrng_stress_all 1320.000s 87713.443us 24 25 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 101.000s 6872.300us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 26.000s 1867.872us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
csrng_sec_cm 8.000s 154.024us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
csrng_sec_cm 8.000s 154.024us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 26.000s 1846.973us 200 200 100.00
csrng_err 13.000s 23.202us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 142.000s 4152.400us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 8 test runs
csrng_stress_all_with_rand_reset 43588076037237058265353848741409404521711867105495487274287673947569333369107 165
UVM_INFO @ 899546085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 63870427755489358592455893818405683981150620230531489858614106762862801394301 114
UVM_INFO @ 9933135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 65079115235564334863400786539501137296866830647483661092009774314987515805715 136
UVM_INFO @ 2020169354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 23474557533143085934654757202489179981092753002242842912621241742709976556880 170
UVM_INFO @ 1358905249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 20054047184362147113231656908887087663185705341106673923305284037383292690869 143
UVM_INFO @ 5738527153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 110992000283013692745640275969576511627163944792200352439280363116645824533973 107
UVM_INFO @ 12322871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 68587512791861085495735524091705365339105392255366467280950365939996331204921 191
UVM_INFO @ 1103558285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 106056621925488940152344347488647842647120951257793321114043700820127785421334 112
UVM_INFO @ 17890085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:180) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 3 test runs
csrng_stress_all_with_rand_reset 110312257390461929406446890118577185524102792852251071702243258979988426229053 165
UVM_INFO @ 907590483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 109086113670591493171275869455010730990544213175442592846116904595226644846753 267
UVM_INFO @ 4152400409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 74951716678202714944333016132141309977533167054438326988460363946119977837715 113
UVM_INFO @ 1292419387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---