Simulation Results: edn/edn0

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.78 %
  • code
  • 95.55 %
  • assert
  • 98.92 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.79 %
  • toggle
  • 97.12 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
93.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.370s 29.414us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.170s 45.520us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.250s 12.881us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.490s 298.122us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.370s 15.663us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.700s 112.899us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.250s 12.881us 5 5 100.00
edn_csr_aliasing 1.370s 15.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.250s 406.375us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.250s 406.375us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.250s 406.375us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.550s 24.663us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.840s 37.298us 200 200 100.00
errs 100 100 100.00
edn_err 2.110s 50.245us 100 100 100.00
disable 100 100 100.00
edn_disable 1.310s 14.272us 50 50 100.00
edn_disable_auto_req_mode 1.980s 55.002us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 6.250s 800.184us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.250s 13.355us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.510s 23.692us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.030s 439.793us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.030s 439.793us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.170s 45.520us 1 1 100.00
edn_csr_rw 1.250s 12.881us 5 5 100.00
edn_csr_aliasing 1.370s 15.663us 1 1 100.00
edn_same_csr_outstanding 1.650s 273.054us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.170s 45.520us 1 1 100.00
edn_csr_rw 1.250s 12.881us 5 5 100.00
edn_csr_aliasing 1.370s 15.663us 1 1 100.00
edn_same_csr_outstanding 1.650s 273.054us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 11.130s 570.709us 5 5 100.00
edn_tl_intg_err 3.580s 140.138us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.290s 29.924us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.840s 37.298us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.130s 570.709us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.130s 570.709us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 11.130s 570.709us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 11.130s 570.709us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.840s 37.298us 200 200 100.00
edn_sec_cm 11.130s 570.709us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.840s 37.298us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.580s 140.138us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 28 30 93.33
edn_stress_all_with_rand_reset 149.300s 10938.516us 28 30 93.33

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 2 test runs
edn_stress_all_with_rand_reset 64386047379440631646714832067123430985064237743323914419546916115600085932229 164
UVM_INFO @ 10938516405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 41120219742619838213952871551332861729408491521581034469531582116112845415718 129
UVM_INFO @ 10689533545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---