Simulation Results: edn/edn1

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.52 %
  • code
  • 95.63 %
  • assert
  • 98.70 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.69 %
  • toggle
  • 96.08 %
  • FSM
  • 94.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.57%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.230s 19.494us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.020s 29.601us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.100s 14.493us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.750s 307.339us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.140s 12.301us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.570s 57.601us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.100s 14.493us 5 5 100.00
edn_csr_aliasing 1.140s 12.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.830s 706.442us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.830s 706.442us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.830s 706.442us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.350s 27.621us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.810s 305.395us 200 200 100.00
errs 100 100 100.00
edn_err 1.630s 28.213us 100 100 100.00
disable 100 100 100.00
edn_disable 1.260s 13.555us 50 50 100.00
edn_disable_auto_req_mode 1.810s 53.358us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 8.330s 742.278us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.150s 18.735us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.090s 68.505us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.120s 500.131us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.120s 500.131us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.020s 29.601us 1 1 100.00
edn_csr_rw 1.100s 14.493us 5 5 100.00
edn_csr_aliasing 1.140s 12.301us 1 1 100.00
edn_same_csr_outstanding 1.430s 88.090us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.020s 29.601us 1 1 100.00
edn_csr_rw 1.100s 14.493us 5 5 100.00
edn_csr_aliasing 1.140s 12.301us 1 1 100.00
edn_same_csr_outstanding 1.430s 88.090us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
edn_sec_cm 5.110s 375.867us 5 5 100.00
edn_tl_intg_err 15.160s 3574.438us 24 25 96.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.200s 31.655us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.810s 305.395us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.110s 375.867us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.110s 375.867us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.110s 375.867us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.110s 375.867us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.810s 305.395us 200 200 100.00
edn_sec_cm 5.110s 375.867us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.810s 305.395us 200 200 100.00
sec_cm_tile_link_bus_integrity 24 25 96.00
edn_tl_intg_err 15.160s 3574.438us 24 25 96.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 30 100.00
edn_stress_all_with_rand_reset 118.690s 34694.620us 30 30 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [edn_common_vseq] Expected alert (fatal_alert) did not fire in * cycles. 1 test run
edn_tl_intg_err 94248880430397857894942389643631529829676482955006379864122436164406682404137 233
UVM_INFO @ 768194244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---