Simulation Results: gpio

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.25 %
  • code
  • 94.91 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 80.52 %
Validation stages
V1
100.00%
V2
94.27%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 1.560s 1342.683us 10 10 100.00
gpio_smoke_no_pullup_pulldown 1.650s 983.749us 10 10 100.00
gpio_smoke_en_cdc_prim 1.310s 189.414us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.610s 90.717us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 0.680s 58.809us 1 1 100.00
csr_rw 5 5 100.00
gpio_csr_rw 0.730s 18.560us 5 5 100.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 1.190s 162.983us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 0.700s 44.874us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 0.920s 21.861us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
gpio_csr_rw 0.730s 18.560us 5 5 100.00
gpio_csr_aliasing 0.700s 44.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.740s 304.771us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.290s 79.775us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.110s 517.295us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 1.480s 195.058us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 2.200s 407.927us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 2.590s 369.150us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 15.720s 503.012us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 4.720s 1211.338us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.060s 306.143us 10 10 100.00
stress_all 1 10 10.00
gpio_stress_all 73.970s 4247.758us 1 10 10.00
alert_test 10 10 100.00
gpio_alert_test 0.690s 14.651us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 0.800s 88.148us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 2.880s 706.784us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 2.880s 706.784us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
gpio_csr_rw 0.730s 18.560us 5 5 100.00
gpio_same_csr_outstanding 0.860s 72.517us 5 5 100.00
gpio_csr_aliasing 0.700s 44.874us 1 1 100.00
gpio_csr_hw_reset 0.680s 58.809us 1 1 100.00
tl_d_partial_access 12 12 100.00
gpio_csr_rw 0.730s 18.560us 5 5 100.00
gpio_same_csr_outstanding 0.860s 72.517us 5 5 100.00
gpio_csr_aliasing 0.700s 44.874us 1 1 100.00
gpio_csr_hw_reset 0.680s 58.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
gpio_tl_intg_err 1.540s 146.456us 25 25 100.00
gpio_sec_cm 1.050s 119.677us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
gpio_tl_intg_err 1.540s 146.456us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 8 10 80.00
gpio_rand_straps 0.760s 21.057us 8 10 80.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 11.270s 2055.153us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:211) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 11 test runs
gpio_stress_all 84218114525923901129374673016661582861075109965952711518941775122218365162935 323
UVM_INFO @ 2410680818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 102306629008933443082651885240454342490589882987329863476039977426073908333794 698
UVM_INFO @ 960185964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 21734380285721233289947170759452532000456994839857689121710182215193965000998 427
UVM_INFO @ 3294516453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 87949147830561646017417784791367702058043054250880875560972301474090322752743 82
UVM_INFO @ 76467264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 111259873586214705967449850100781643239955491495210682142064663603992892760396 1150
UVM_INFO @ 19088575938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 109738664632602832155207319496180702568063845082300376164265169111009212710278 81
UVM_INFO @ 3679819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 11684732410845048090386048252427539470605269064853725096401105284569511845800 1957
UVM_INFO @ 4247757619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 14666172730923393470160807738891742444821200890643503306176747804741228184231 184
UVM_INFO @ 1484175379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 34612037318500851660328703012041995632221009474218398175272666842118893657328 82
UVM_INFO @ 287634509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 100060526712650834069406488835106674775929790463583311753343256108866082281987 81
UVM_INFO @ 1464372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 37918362735162279652045511790892083585248606859659818291183835984126942411924 660
UVM_INFO @ 2288286532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [gpio_common_vseq] Check failed (vseq_done) 6 test runs
gpio_stress_all_with_rand_reset 5037565486663527338594971533378867006015045334634159159954805065598390344070 304
UVM_INFO @ 859611063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 35005581819253741677258919031004954704454822986219901222477702516372433240049 132
UVM_INFO @ 2055153336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 110283107314721690650933939257053330170347875617275564385257280454034785576783 215
UVM_INFO @ 2369080884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 114310117447697850068803616237542327025754915007118358452192063735049430798970 86
UVM_INFO @ 4981603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 13155703431577627313875880317945407451664812005829521021489479747729691452904 86
UVM_INFO @ 1265195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 55067686179977714943247589418068565376697168842238885558896386543325098657806 90
UVM_INFO @ 21442208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 4 test runs
gpio_stress_all_with_rand_reset 67825682636588525120088760527196402696610360480190044974177010136534551860199 84
UVM_INFO @ 70389347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66197945609608136657097484347349969718571096100161514343716607443935538290666 154
UVM_INFO @ 495430680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 51834951869487816609300378966181629263328530934953998280086605086738677718675 395
UVM_INFO @ 466407088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 51729931999138152834333903299387838766776749042330194819889243477511150347770 84
UVM_INFO @ 28752327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---