Simulation Results: hmac

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.97 %
  • code
  • 87.70 %
  • assert
  • 97.60 %
  • func
  • 99.62 %
  • line
  • 99.64 %
  • branch
  • 99.35 %
  • cond
  • 96.30 %
  • toggle
  • 46.17 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
99.83%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 18.260s 21704.411us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.830s 22.809us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.190s 64.998us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.010s 1220.966us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 0.990s 90.442us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 631.800s 246840.555us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.190s 64.998us 5 5 100.00
hmac_csr_aliasing 0.990s 90.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 119.550s 15259.986us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 93.710s 22057.943us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 250.560s 22429.947us 30 30 100.00
hmac_test_sha384_vectors 530.130s 43825.264us 75 75 100.00
hmac_test_sha512_vectors 514.100s 20285.484us 75 75 100.00
hmac_test_hmac256_vectors 15.360s 487.042us 50 50 100.00
hmac_test_hmac384_vectors 14.530s 414.734us 60 60 100.00
hmac_test_hmac512_vectors 17.950s 1924.962us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 32.550s 13732.341us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1614.300s 19029.566us 10 10 100.00
error 10 10 100.00
hmac_error 120.320s 76716.097us 10 10 100.00
wipe_secret 9 10 90.00
hmac_wipe_secret 143.240s 200000.000us 9 10 90.00
save_and_restore 155 155 100.00
hmac_smoke 18.260s 21704.411us 10 10 100.00
hmac_long_msg 119.550s 15259.986us 10 10 100.00
hmac_back_pressure 93.710s 22057.943us 25 25 100.00
hmac_datapath_stress 1614.300s 19029.566us 10 10 100.00
hmac_burst_wr 32.550s 13732.341us 50 50 100.00
hmac_stress_all 4050.180s 261755.942us 50 50 100.00
fifo_empty_status_interrupt 429 430 99.77
hmac_smoke 18.260s 21704.411us 10 10 100.00
hmac_long_msg 119.550s 15259.986us 10 10 100.00
hmac_back_pressure 93.710s 22057.943us 25 25 100.00
hmac_datapath_stress 1614.300s 19029.566us 10 10 100.00
hmac_wipe_secret 143.240s 200000.000us 9 10 90.00
hmac_test_sha256_vectors 250.560s 22429.947us 30 30 100.00
hmac_test_sha384_vectors 530.130s 43825.264us 75 75 100.00
hmac_test_sha512_vectors 514.100s 20285.484us 75 75 100.00
hmac_test_hmac256_vectors 15.360s 487.042us 50 50 100.00
hmac_test_hmac384_vectors 14.530s 414.734us 60 60 100.00
hmac_test_hmac512_vectors 17.950s 1924.962us 75 75 100.00
wide_digest_configurable_key_length 539 540 99.81
hmac_smoke 18.260s 21704.411us 10 10 100.00
hmac_long_msg 119.550s 15259.986us 10 10 100.00
hmac_back_pressure 93.710s 22057.943us 25 25 100.00
hmac_datapath_stress 1614.300s 19029.566us 10 10 100.00
hmac_burst_wr 32.550s 13732.341us 50 50 100.00
hmac_error 120.320s 76716.097us 10 10 100.00
hmac_wipe_secret 143.240s 200000.000us 9 10 90.00
hmac_test_sha256_vectors 250.560s 22429.947us 30 30 100.00
hmac_test_sha384_vectors 530.130s 43825.264us 75 75 100.00
hmac_test_sha512_vectors 514.100s 20285.484us 75 75 100.00
hmac_test_hmac256_vectors 15.360s 487.042us 50 50 100.00
hmac_test_hmac384_vectors 14.530s 414.734us 60 60 100.00
hmac_test_hmac512_vectors 17.950s 1924.962us 75 75 100.00
hmac_stress_all 4050.180s 261755.942us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 4050.180s 261755.942us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.920s 27.993us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.900s 57.184us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.070s 748.351us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.070s 748.351us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 0.830s 22.809us 1 1 100.00
hmac_csr_rw 1.190s 64.998us 5 5 100.00
hmac_csr_aliasing 0.990s 90.442us 1 1 100.00
hmac_same_csr_outstanding 1.970s 333.893us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 0.830s 22.809us 1 1 100.00
hmac_csr_rw 1.190s 64.998us 5 5 100.00
hmac_csr_aliasing 0.990s 90.442us 1 1 100.00
hmac_same_csr_outstanding 1.970s 333.893us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.490s 232.842us 5 5 100.00
hmac_tl_intg_err 4.740s 1043.589us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.740s 1043.589us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 18.260s 21704.411us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 5.770s 532.834us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 634.290s 7762.357us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.400s 231.138us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
hmac_wipe_secret 46055813797053496687895761010181180657614817999472563829509579362497182340230 34735
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---