Simulation Results: lc_ctrl/volatile_unlock_disabled

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.31 %
  • code
  • 85.67 %
  • assert
  • 94.83 %
  • func
  • 96.42 %
  • line
  • 97.28 %
  • branch
  • 93.90 %
  • cond
  • 81.56 %
  • toggle
  • 88.33 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
94.61%
V2S
99.33%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.070s 265.434us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.100s 42.415us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.240s 18.765us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.960s 58.611us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 48.175us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.590s 69.565us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.240s 18.765us 5 5 100.00
lc_ctrl_csr_aliasing 1.280s 48.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 7.560s 783.833us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 10.720s 344.538us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.210s 15.726us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 2.800s 114.097us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 10.290s 611.577us 20 20 100.00
security_escalation 121 140 86.43
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_prog_failure 2.800s 114.097us 20 20 100.00
lc_ctrl_errors 10.290s 611.577us 20 20 100.00
lc_ctrl_security_escalation 8.330s 357.459us 20 20 100.00
lc_ctrl_jtag_state_failure 33.170s 2566.984us 9 20 45.00
lc_ctrl_jtag_prog_failure 11.120s 5890.647us 16 20 80.00
lc_ctrl_jtag_errors 51.590s 20062.173us 16 20 80.00
jtag_access 201 210 95.71
lc_ctrl_jtag_smoke 9.320s 598.798us 20 20 100.00
lc_ctrl_jtag_state_post_trans 14.690s 438.359us 19 20 95.00
lc_ctrl_jtag_prog_failure 11.120s 5890.647us 16 20 80.00
lc_ctrl_jtag_errors 51.590s 20062.173us 16 20 80.00
lc_ctrl_jtag_access 10.890s 1669.376us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 22.830s 7654.603us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.710s 298.539us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.100s 135.415us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 15.730s 20360.868us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 3.170s 297.917us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.860s 223.621us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.380s 273.191us 10 10 100.00
lc_ctrl_jtag_alert_test 1.880s 64.894us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 14.730s 4644.943us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.260s 49.929us 10 10 100.00
stress_all 7 10 70.00
lc_ctrl_stress_all 252.430s 10848.121us 7 10 70.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.260s 69.255us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.570s 546.487us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.570s 546.487us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.100s 42.415us 1 1 100.00
lc_ctrl_csr_rw 1.240s 18.765us 5 5 100.00
lc_ctrl_csr_aliasing 1.280s 48.175us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.870s 321.620us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.100s 42.415us 1 1 100.00
lc_ctrl_csr_rw 1.240s 18.765us 5 5 100.00
lc_ctrl_csr_aliasing 1.280s 48.175us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.870s 321.620us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
lc_ctrl_tl_intg_err 2.720s 129.069us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 2.720s 129.069us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 10.720s 344.538us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.100s 1228.241us 20 20 100.00
lc_ctrl_sec_cm 8.810s 1057.317us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 8.330s 357.459us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 7.560s 783.833us 20 20 100.00
lc_ctrl_jtag_state_post_trans 14.690s 438.359us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.960s 874.715us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.960s 874.715us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.230s 1946.312us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.010s 505.725us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.010s 505.725us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 49.000s 30426.531us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 17 test runs
lc_ctrl_jtag_state_failure 4901393672212698493955007819690433156001975657990791153867000902507796399394 710
UVM_INFO @ 1046699819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107048329806519776099627022491297860717716582181127597824189772761246184988652 3241
UVM_INFO @ 3696392211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 76463726243474130022640061590584417740542159069816718709340010095244252147591 783
UVM_INFO @ 486910617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 107741536769539601516747643864605191541267565026987583918038432383348403568317 3099
UVM_INFO @ 2854091314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 51390286225728057327572752537302432138387248587539350779967915601614834555424 1463
UVM_INFO @ 3933232555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 83175822334189237772301753165046024262130605473675775740396984308447560669537 386
UVM_INFO @ 692519785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 31291329534218779544301047032718009091405459677522145820103190612620509533555 4592
UVM_INFO @ 8124574672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 90358984132817185585015517707451838464555675375129010726896754829881713029698 2156
UVM_INFO @ 1945608735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 61154437807109145826144778178828326735849687678317849343944454474256845153534 1364
UVM_INFO @ 742377144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 42854019734845989696308691045229415960929092783846390195478068015715821202181 3698
UVM_INFO @ 20242985122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 4542645648692362866559956541734988472581904325180040612219574838316507634913 2292
UVM_INFO @ 1812016344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 18107945496105288948978936117294926682652756334906811200891382705859779587016 303
UVM_INFO @ 611717836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 86257293820859847026302987474988125602131920412990925728778759904792862459655 300
UVM_INFO @ 811661452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 60142930506340414170448947820638419679341728930694713419834111601219974245958 540
UVM_INFO @ 2598995818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 111480476865763149493021766785857350106726087133143059351096793988748304499806 402
UVM_INFO @ 373009062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 100680613499164344386241201196888411707996705634420387882868967730483521286779 1102
UVM_INFO @ 1890166594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 68721308570819587089633721733515479219647785514627974149554997863249901294960 1740
UVM_INFO @ 1283903006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 9 test runs
lc_ctrl_jtag_errors 46385133884728904529726965467925113110262628826879271696423758770245956400966 1678
UVM_INFO @ 5180543967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 78925126351406724186785407235717875893723090346355326264414456443040403259425 929
UVM_INFO @ 5890646870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 83387559170421795244789413006957544492895247413231667302111669339420288702956 458
UVM_INFO @ 1856968111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 52603579890091792793151744655585176181937522926736638138608480321500283199524 2930
UVM_INFO @ 1607496437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 12445564037078544702440088021405249793655018973399294507303364217068467676328 802
UVM_INFO @ 1135729413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 68580542204629308085837907865529326406399227239320891928434228432175065178463 462
UVM_INFO @ 508449556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 33321999831118126247093501330776775655330656876057627445994771495181775353404 3253
UVM_INFO @ 35917076832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 68118588273139500730619404040946625602270662046309536714471603358321720517193 249
UVM_INFO @ 81625961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 42273853767406477904064713575632052645434398117540902252321082409210125781420 3090
UVM_INFO @ 2399144582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 9837102704684545012914238988955385922213158434740823226863189804977021660297 3615
UVM_INFO @ 9426573769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51688743872733739416248993581873497103807324075497242505022490946189436012739 169
UVM_INFO @ 107773957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113418794533838623729705548632994416299844061095248552611287353762622412695249 2717
UVM_INFO @ 11745627680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13893158392876919966700725720271728526944109594245824310062628971663389165338 5689
UVM_INFO @ 30426531343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---