Simulation Results: lc_ctrl/volatile_unlock_enabled

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.33 %
  • code
  • 85.93 %
  • assert
  • 94.83 %
  • func
  • 96.24 %
  • line
  • 97.26 %
  • branch
  • 94.00 %
  • cond
  • 81.83 %
  • toggle
  • 88.33 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
94.85%
V2S
96.67%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.460s 482.163us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.030s 16.756us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.240s 37.012us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.630s 391.566us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 73.762us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.780s 24.619us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.240s 37.012us 5 5 100.00
lc_ctrl_csr_aliasing 1.220s 73.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 6.960s 102.887us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.650s 294.346us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.100s 76.932us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 2.870s 417.091us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 10.270s 796.061us 19 20 95.00
security_escalation 126 140 90.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_prog_failure 2.870s 417.091us 20 20 100.00
lc_ctrl_errors 10.270s 796.061us 19 20 95.00
lc_ctrl_security_escalation 7.810s 927.721us 20 20 100.00
lc_ctrl_jtag_state_failure 27.590s 2631.874us 13 20 65.00
lc_ctrl_jtag_prog_failure 7.650s 1192.529us 15 20 75.00
lc_ctrl_jtag_errors 33.100s 13012.799us 19 20 95.00
jtag_access 199 210 94.76
lc_ctrl_jtag_smoke 7.120s 5369.263us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.920s 926.689us 15 20 75.00
lc_ctrl_jtag_prog_failure 7.650s 1192.529us 15 20 75.00
lc_ctrl_jtag_errors 33.100s 13012.799us 19 20 95.00
lc_ctrl_jtag_access 8.820s 2788.750us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 16.190s 1653.480us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.280s 646.743us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.330s 258.099us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 14.530s 1594.336us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 2.440s 113.527us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.450s 50.932us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.420s 183.768us 10 10 100.00
lc_ctrl_jtag_alert_test 1.640s 51.400us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 29.150s 15114.751us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.170s 20.078us 10 10 100.00
stress_all 7 10 70.00
lc_ctrl_stress_all 178.730s 8343.753us 7 10 70.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.200s 19.141us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.320s 151.770us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.320s 151.770us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.030s 16.756us 1 1 100.00
lc_ctrl_csr_rw 1.240s 37.012us 5 5 100.00
lc_ctrl_csr_aliasing 1.220s 73.762us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.310s 24.114us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.030s 16.756us 1 1 100.00
lc_ctrl_csr_rw 1.240s 37.012us 5 5 100.00
lc_ctrl_csr_aliasing 1.220s 73.762us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.310s 24.114us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
lc_ctrl_tl_intg_err 2.760s 238.888us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 2.760s 238.888us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.650s 294.346us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.730s 3679.139us 20 20 100.00
lc_ctrl_sec_cm 12.280s 1880.520us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.810s 927.721us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 35 40 87.50
lc_ctrl_state_post_trans 6.960s 102.887us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.920s 926.689us 15 20 75.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.030s 928.271us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.030s 928.271us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 9.490s 635.312us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.600s 1286.684us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.600s 1286.684us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 53.010s 14486.118us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 16 test runs
lc_ctrl_stress_all_with_rand_reset 22497964744374786205432079721441683853352567909081073362789527327703722610951 1968
UVM_INFO @ 4534610080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8086578787083847902155622591129791685230509086431031709637127953130096376190 4411
UVM_INFO @ 1786748370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 111711338642598680257541407257043014635916916808590853963063469617811299534617 4184
UVM_INFO @ 12910905339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 55502322249080019949789636678454194804870121308153441689332329599396870756456 289
UVM_INFO @ 574399629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 27629144314963310282669371928545541295663242689345539973732344338255093793814 903
UVM_INFO @ 870485484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 16871281467615202261322557306148105390409962058380983772324200875734038012535 742
UVM_INFO @ 858085987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 42991802001787371584794966673472181417782009291503884900997297344299776502918 1360
UVM_INFO @ 461974093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 111777487114058181687252252034033827669705497448228477801034934877901049579554 346
UVM_INFO @ 618945799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 33959984010289231680275400238374865453818112870950825729262549360917999974572 1424
UVM_INFO @ 3830618378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 16059734053719823737420118585852408636922380740657706060099919986293722537270 474
UVM_INFO @ 2326584280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 56962682258244480086584498128711613399229013485616771071243812240052337854690 1261
UVM_INFO @ 1017866027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 73586667271349045134353480991557427423383336976235182941791376491347528363319 397
UVM_INFO @ 143360610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 10894926019513579260494523114519453733736268665587988795742256583059731295679 209
UVM_INFO @ 28830206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 40425339771659119172809629988404581250273881403291810667102832977870310396763 613
UVM_INFO @ 320277871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 76425091104168280741215579911200792870887612507146519366597704152732974275308 212
UVM_INFO @ 129790934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 97839727225710309998872124773932187732416382713747880942144055549718276608479 298
UVM_INFO @ 197703353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 6 test runs
lc_ctrl_jtag_errors 15638139625312941345517288670829398232439236902461114134521612546827794134808 794
UVM_INFO @ 4324597161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 69721399808521495654135433023633408152889199751036727848745792575637967977474 631
UVM_INFO @ 661126349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 28672361264680694569846903719990878197752144995418170545584843080448232099587 336
UVM_INFO @ 2370993148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 13105799770915154516861801425150998853599012090820770969838389548864585577870 546
UVM_INFO @ 521308821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 77267710210504897087052526070333891265378393470528124005674972818779012897257 419
UVM_INFO @ 393457563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 30613893693955172766954290713324751078875189452722580637486752131721346521706 593
UVM_INFO @ 548966225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 72844795524662446965307093181284161258384105571645327147661670117522062265 4202
UVM_INFO @ 1087656267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19501422657595510617980855796235442197616994938244962228674339141578551334320 2017
UVM_INFO @ 1389180495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47314862465556243205749040131090725782845418747054801620604420347299501832130 168
UVM_INFO @ 220171046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61779884212923968473596773078634209909620992337457289427046799324224860017316 258
UVM_INFO @ 1709671322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_stress_all 108710547554508214027757614333782298683877554605773059336932078829914695935233 458
UVM_INFO @ 966416349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 108079724333231679660327990457560088653801158274706545871606155149533494024488 1830
UVM_INFO @ 264213143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:933) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 9427929702497706002786810145877608374117743745417205391456552507816547270938 4777
UVM_INFO @ 1394982870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---