Simulation Results: otbn

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.20 %
  • code
  • 82.62 %
  • assert
  • 96.97 %
  • func
  • 100.00 %
  • block
  • 97.83 %
  • line
  • 98.05 %
  • branch
  • 82.25 %
  • toggle
  • 82.58 %
  • FSM
  • 67.61 %
Validation stages
V1
99.15%
V2
94.71%
V2S
97.87%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 18.000s 845.654us 1 1 100.00
otbn_smoke_vectorized 12.000s 60.270us 1 1 100.00
single_binary 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 23.259us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 5.000s 19.677us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 12.000s 571.759us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 12.285us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 15.000s 49.451us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 5.000s 19.677us 5 5 100.00
otbn_csr_aliasing 6.000s 12.285us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 148.000s 1521.863us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 27.000s 657.089us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 71.000s 141.735us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 111.000s 232.459us 1 1 100.00
wfi 3 7 42.86
otbn_wfi_smoke 6.000s 11.554us 0 1 0.00
otbn_wfi_sec_wipe 11.000s 28.373us 3 5 60.00
otbn_wfi_back_to_back 6.000s 18.815us 0 1 0.00
back_to_back 10 10 100.00
otbn_multi 227.000s 2660.021us 10 10 100.00
stress_all 8 10 80.00
otbn_stress_all 134.000s 2420.465us 8 10 80.00
lc_escalation 58 60 96.67
otbn_escalate 28.000s 203.634us 58 60 96.67
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 11.000s 16.044us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 72.000s 668.644us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 12.000s 197.191us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 8.000s 23.999us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 10.000s 133.215us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 10.000s 133.215us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 5.000s 23.259us 1 1 100.00
otbn_csr_rw 5.000s 19.677us 5 5 100.00
otbn_csr_aliasing 6.000s 12.285us 1 1 100.00
otbn_same_csr_outstanding 6.000s 207.144us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 5.000s 23.259us 1 1 100.00
otbn_csr_rw 5.000s 19.677us 5 5 100.00
otbn_csr_aliasing 6.000s 12.285us 1 1 100.00
otbn_same_csr_outstanding 6.000s 207.144us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 17.000s 31.041us 10 10 100.00
otbn_dmem_err 24.000s 154.163us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 29.000s 133.403us 5 5 100.00
otbn_controller_ispr_rdata_err 30.000s 234.281us 5 5 100.00
otbn_mac_bignum_acc_err 16.000s 36.969us 5 5 100.00
otbn_urnd_err 8.000s 14.268us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 12.000s 32.458us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 10.000s 15.726us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 12.000s 114.017us 9 10 90.00
tl_intg_err 30 30 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
otbn_tl_intg_err 43.000s 200.484us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 69.000s 926.468us 5 5 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 18.000s 845.654us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 24.000s 154.163us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 17.000s 31.041us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 43.000s 200.484us 25 25 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 28.000s 203.634us 58 60 96.67
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 17.000s 31.041us 10 10 100.00
otbn_dmem_err 24.000s 154.163us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 16.044us 4 5 80.00
otbn_illegal_mem_acc 12.000s 32.458us 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 17.000s 31.041us 10 10 100.00
otbn_dmem_err 24.000s 154.163us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 16.044us 4 5 80.00
otbn_illegal_mem_acc 12.000s 32.458us 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 28.000s 203.634us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 17.000s 31.041us 10 10 100.00
otbn_dmem_err 24.000s 154.163us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 16.044us 4 5 80.00
otbn_illegal_mem_acc 12.000s 32.458us 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 15.000s 33.886us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 23.000s 67.558us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 103.000s 250.275us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 103.000s 250.275us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 17.000s 26.862us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 8 10 80.00
otbn_rf_bignum_intg_err 14.000s 212.961us 8 10 80.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 25.000s 96.187us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 25.000s 96.187us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 32.000s 56.499us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 227.000s 2660.021us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 19.000s 25.248us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 56.000s 252.351us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 591.000s 3397.050us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
otbn_stress_all_with_rand_reset 18.000s 388.553us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 9 test runs
otbn_stress_all_with_rand_reset 16924247172308783692410999838732546649443293206011357586164671045409498157740 146
UVM_INFO @ 23531192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 19673707078283629540019124397672546683195187707216605835100557643278731382440 148
UVM_INFO @ 25075188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 95916913325963908527324638637908907689851167634627747730370456134607316839327 167
UVM_INFO @ 388552604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 9236367577131143478816612965084771320464498642172675202282844727019430420482 148
UVM_INFO @ 65270353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 29317937892051345397627460917076067024935982828405347546270840401730608818650 149
UVM_INFO @ 35678467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 92106275540144749556344694430138068605833247790064258320931898169209232248647 162
UVM_INFO @ 25010115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 33356838972054705582629891246901374901613027610366080406204254398828310398533 146
UVM_INFO @ 124424315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 63527538222882304192626524856291646868457924260939299932107887188778893586422 148
UVM_INFO @ 95153928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 92165671610620324670455316902518201909040258492411925525240335418479370623428 146
UVM_INFO @ 10971877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. 2 test runs
otbn_wfi_smoke 110069855989877211418987180537862966043336304097397238167745882847066325825809 113
UVM_INFO @ 11554154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_back_to_back 64372538968496936900944954816394324128940919593696969315261612987666736459350 109
UVM_INFO @ 18814820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value. 2 test runs
otbn_wfi_sec_wipe 29959455624831090887279801267433590565553115932949353478790393223208135233608 114
UVM_FATAL @ 18259065 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 18259065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_sec_wipe 42468882816289422045600212049663481453300377269185689900558447180890748652540 113
UVM_FATAL @ 4531758 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 4531758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_zero_state_err_urnd 15863820588911463976551056941468936810584944374553638606430588686014586918490 107
UVM_ERROR @ 6855390 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 6855390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 14591633766757055994340200780790741415306459202468591725032651539879111182073 115
UVM_ERROR @ 14417482 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 14417482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 2 test runs
otbn_partial_wipe 58921083220561152529213052620548349085881726816827842845929174341223023465925 115
UVM_INFO @ 7983718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 6725406910788444928277464142069771402325837918018153130035848509265666138564 105
UVM_INFO @ 6331014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,158): Assertion NoModelErrs has failed 1 test run
otbn_rf_bignum_intg_err 82982003837073450217112357304129536577660327056150980307523508886527412594281 122
UVM_ERROR @ 15483411 ps: (otbn_model_if.sv:158) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 15483411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_stress_all 74312037388385225662028466725214943864240162780956747147445094299544003071358 333
UVM_INFO @ 72716527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_bignum_intg_err 74613317504084286240428303035237725163139501876518599496758492530279636899900 110
UVM_INFO @ 19500281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:352) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 18223074696442499840206800154077919734672002203381207639443798741742396192198 144
UVM_INFO @ 3303794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_rnd_if.sv,175): Assertion EdgePREFETCHINGToFULL_A has failed (* cycles, starting * PS) 1 test run
otbn_stress_all 19521879930056732975534662230373496917694988147012834492819981572180244936551 378
UVM_ERROR @ 383238561 ps: (otbn_rnd_if.sv:175) [ASSERT FAILED] EdgePREFETCHINGToFULL_A
UVM_INFO @ 383238561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_single 87247796095929322926304316363794465308238035223165262388287958824576154300611 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1