Simulation Results

Simulation Results: otp_ctrl

19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
90.85 %

code
85.40 %

assert
95.47 %

func
91.68 %

line
90.29 %

branch
86.80 %

cond
93.98 %

toggle
92.55 %

FSM
63.37 %

Validation stages

V1		92.31%
V2		77.16%
V2S		77.58%
V3		14.85%

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	1.500s	108.682us	1	1	100.00
smoke				10	10	100.00
	otp_ctrl_smoke	16.320s	5255.858us	10	10	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	2.540s	125.150us	1	1	100.00
csr_rw				5	5	100.00
	otp_ctrl_csr_rw	3.210s	535.019us	5	5	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	6.410s	649.397us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	1.900s	120.863us	1	1	100.00
csr_mem_rw_with_rand_reset				3	5	60.00
	otp_ctrl_csr_mem_rw_with_rand_reset	3.650s	210.859us	3	5	60.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otp_ctrl_csr_rw	3.210s	535.019us	5	5	100.00
	otp_ctrl_csr_aliasing	1.900s	120.863us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	2.030s	520.926us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.380s	43.092us	1	1	100.00

581/753 passed

77.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				1	1	100.00
	otp_ctrl_partition_walk	13.020s	395.380us	1	1	100.00
init_fail				257	300	85.67
	otp_ctrl_init_fail	7.420s	1768.257us	257	300	85.67
partition_check				37	60	61.67
	otp_ctrl_background_chks	34.810s	6648.076us	8	10	80.00
	otp_ctrl_check_fail	33.180s	7782.620us	29	50	58.00
regwen_during_otp_init				30	30	100.00
	otp_ctrl_regwen	14.940s	4257.641us	30	30	100.00
partition_lock				30	30	100.00
	otp_ctrl_dai_lock	58.740s	20601.193us	30	30	100.00
interface_key_check				8	10	80.00
	otp_ctrl_parallel_key_req	40.810s	4193.053us	8	10	80.00
lc_interactions				138	210	65.71
	otp_ctrl_parallel_lc_req	25.310s	9836.623us	10	10	100.00
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
otp_dai_errors				5	25	20.00
	otp_ctrl_dai_errs	20.780s	581.634us	5	25	20.00
otp_macro_errors				4	10	40.00
	otp_ctrl_macro_errs	25.710s	3397.407us	4	10	40.00
test_access				10	10	100.00
	otp_ctrl_test_access	38.640s	2854.407us	10	10	100.00
stress_all				4	10	40.00
	otp_ctrl_stress_all	185.910s	17650.164us	4	10	40.00
intr_test				10	10	100.00
	otp_ctrl_intr_test	2.920s	544.923us	10	10	100.00
alert_test				10	10	100.00
	otp_ctrl_alert_test	2.850s	240.856us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otp_ctrl_tl_errors	13.360s	3499.916us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otp_ctrl_tl_errors	13.360s	3499.916us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otp_ctrl_csr_hw_reset	2.540s	125.150us	1	1	100.00
	otp_ctrl_csr_rw	3.210s	535.019us	5	5	100.00
	otp_ctrl_csr_aliasing	1.900s	120.863us	1	1	100.00
	otp_ctrl_same_csr_outstanding	3.540s	1076.924us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otp_ctrl_csr_hw_reset	2.540s	125.150us	1	1	100.00
	otp_ctrl_csr_rw	3.210s	535.019us	5	5	100.00
	otp_ctrl_csr_aliasing	1.900s	120.863us	1	1	100.00
	otp_ctrl_same_csr_outstanding	3.540s	1076.924us	5	5	100.00

V2S

512/660 passed

77.58 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
tl_intg_err				24	30	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
	otp_ctrl_tl_intg_err	26.740s	4811.784us	20	25	80.00
prim_count_check				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
prim_fsm_check				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_bus_integrity				20	25	80.00
	otp_ctrl_tl_intg_err	26.740s	4811.784us	20	25	80.00
sec_cm_secret_mem_scramble				10	10	100.00
	otp_ctrl_smoke	16.320s	5255.858us	10	10	100.00
sec_cm_part_mem_digest				10	10	100.00
	otp_ctrl_smoke	16.320s	5255.858us	10	10	100.00
sec_cm_dai_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_kdi_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_lci_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_part_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_scrmbl_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_timer_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_dai_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_kdi_seed_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_kdi_entropy_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_lci_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_part_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_scrmbl_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_timer_integ_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_timer_cnsty_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_timer_lfsr_redun				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_dai_fsm_local_esc				132	205	64.39
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_lci_fsm_local_esc				128	200	64.00
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
sec_cm_kdi_fsm_local_esc				128	200	64.00
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
sec_cm_part_fsm_local_esc				132	210	62.86
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
	otp_ctrl_macro_errs	25.710s	3397.407us	4	10	40.00
sec_cm_scrmbl_fsm_local_esc				128	200	64.00
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
sec_cm_timer_fsm_local_esc				132	205	64.39
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_dai_fsm_global_esc				132	205	64.39
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_lci_fsm_global_esc				128	200	64.00
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
sec_cm_kdi_fsm_global_esc				128	200	64.00
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
sec_cm_part_fsm_global_esc				132	210	62.86
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
	otp_ctrl_macro_errs	25.710s	3397.407us	4	10	40.00
sec_cm_scrmbl_fsm_global_esc				128	200	64.00
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
sec_cm_timer_fsm_global_esc				132	205	64.39
	otp_ctrl_parallel_lc_esc	35.040s	3234.670us	128	200	64.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_part_data_reg_integrity				257	300	85.67
	otp_ctrl_init_fail	7.420s	1768.257us	257	300	85.67
sec_cm_part_data_reg_bkgn_chk				29	50	58.00
	otp_ctrl_check_fail	33.180s	7782.620us	29	50	58.00
sec_cm_part_mem_regren				30	30	100.00
	otp_ctrl_dai_lock	58.740s	20601.193us	30	30	100.00
sec_cm_part_mem_sw_unreadable				30	30	100.00
	otp_ctrl_dai_lock	58.740s	20601.193us	30	30	100.00
sec_cm_part_mem_sw_unwritable				30	30	100.00
	otp_ctrl_dai_lock	58.740s	20601.193us	30	30	100.00
sec_cm_lc_part_mem_sw_noaccess				30	30	100.00
	otp_ctrl_dai_lock	58.740s	20601.193us	30	30	100.00
sec_cm_access_ctrl_mubi				30	30	100.00
	otp_ctrl_dai_lock	58.740s	20601.193us	30	30	100.00
sec_cm_token_valid_ctrl_mubi				10	10	100.00
	otp_ctrl_smoke	16.320s	5255.858us	10	10	100.00
sec_cm_lc_ctrl_intersig_mubi				30	30	100.00
	otp_ctrl_dai_lock	58.740s	20601.193us	30	30	100.00
sec_cm_test_bus_lc_gated				10	10	100.00
	otp_ctrl_smoke	16.320s	5255.858us	10	10	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	129.350s	11205.337us	4	5	80.00
sec_cm_direct_access_config_regwen				30	30	100.00
	otp_ctrl_regwen	14.940s	4257.641us	30	30	100.00
sec_cm_check_trigger_config_regwen				10	10	100.00
	otp_ctrl_smoke	16.320s	5255.858us	10	10	100.00
sec_cm_check_config_regwen				10	10	100.00
	otp_ctrl_smoke	16.320s	5255.858us	10	10	100.00
sec_cm_macro_mem_integrity				4	10	40.00
	otp_ctrl_macro_errs	25.710s	3397.407us	4	10	40.00

15/101 passed

14.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				1	1	100.00
	otp_ctrl_low_freq_read	12.060s	8742.386us	1	1	100.00
stress_all_with_rand_reset				14	100	14.00
	otp_ctrl_stress_all_with_rand_reset	120.260s	30293.961us	14	100	14.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:474) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *)				71 test runs
	otp_ctrl_stress_all_with_rand_reset	83347176482568847701484797188245728757550538130750010136459491722118186283363	3111	UVM_INFO @ 2444404759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	12011544705854184818745246260834630867161824906656877519493269246957513531627	1274	UVM_INFO @ 199749614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	38500271496769643696777526359743646463161455220582108858790601561106223485386	253	UVM_INFO @ 1144492694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	92146477410391372135682148789025035640555480731190938189891776300986924514512	5465	UVM_INFO @ 351215574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	65698271667816147832256686537586658208554603330154427923685368639371686648370	6491	UVM_INFO @ 134328791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	15746292182484629362440712961330557697617306431984058098391162753546898474849	12412	UVM_INFO @ 3600168429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	78193564337146269307892646128445230561013288758342304690171707846702569113927	2877	UVM_INFO @ 6187696963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	104949208101345369988196934017883325868162635457287739570587171685274775258690	9405	UVM_INFO @ 269598645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	102146854754806754230513763758586188561164044391829763763614137872544629105880	8118	UVM_INFO @ 714904082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	99365682219188946553285487334325466875447902073613097406747274670430808597872	28562	UVM_INFO @ 41006004919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	80088788263418038541232808165134851219392756747563510943551345786415313927597	1653	UVM_INFO @ 225023326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	8173066758983634552614850762122532218762267967823030233641909982178360619202	2960	UVM_INFO @ 196637183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	94095144535670425015567484530070035552958098843000414471097452867399808155308	4808	UVM_INFO @ 4637293436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	70312087392029517738712568889952115264461889453965949628571638226909597354731	1233	UVM_INFO @ 1491483017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	21011793405995939834858079177997762289056374927375409907867385171019964729359	6620	UVM_INFO @ 2073906660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	95882162788184771319691093774628897192498052955514478366712858289436794587626	4273	UVM_INFO @ 366348158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	10572245224988691166328792625217917320589349187773853479045297610490926679982	3003	UVM_INFO @ 752665503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	585943794465098886536728719711114252306366400501987314605540428574119681016	1333	UVM_INFO @ 1908139017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	23002389598478811765226453617331410137084734549537653110524345527817327525540	8539	UVM_INFO @ 1072751704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	26869392394943910118942248662673747967761097258598206404244895362045151564839	2047	UVM_INFO @ 156185844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	18417547559268520277045738696443281128921614321021915224366564908553008774957	6236	UVM_INFO @ 937479328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	105060182822468008306785120073248475849995472371466207308296702718419004097185	3532	UVM_INFO @ 3667984033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	91823100766475265818837899988337487590861498086079909417079615592966954312218	3348	UVM_INFO @ 839296055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	34885514945690229932337891360034302423787356913424366408843892322762746112040	6350	UVM_INFO @ 463267571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	60300491596441331935471271959134562137361055222174101071482900988138066403625	3162	UVM_INFO @ 251219642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	51972457727489494140657722075170755061449937017347966400761215435235367922666	7024	UVM_INFO @ 707545914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	97096902140820414224351571727011316889069526471889817329141002323709816149807	4515	UVM_INFO @ 1352122638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	64602410233154790744871872941282223368289847241744688490265614690204316282828	2059	UVM_INFO @ 577324001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	110735522424438456928672390968844227046037535713921717458384305673989810349811	2194	UVM_INFO @ 363411152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	77478794611829629442517295743607194209064053575650519187989340444985783328794	789	UVM_INFO @ 1984464577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	41506657746069270538629773300042344824244076585990342295244951186480730338550	496	UVM_INFO @ 222470494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	36162833144020693374351698185276665919549183580532492291381221444573883535965	17152	UVM_INFO @ 8425153743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	90526145360079103788998703130886998932044830238879535145025443699315338966531	1734	UVM_INFO @ 689265671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	60278923026071098267953660367227718580856344110702522974225003976221204764790	10057	UVM_INFO @ 1016912016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	20564704925672442354026210605568647874586274984312157560936304708283845095424	2128	UVM_INFO @ 1033703873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	92079131234954364492689450635076354160986605438720742472501667958092732083394	3226	UVM_INFO @ 1314416741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	59751905989432017238746363275847192278969672520592285083373970225896252735527	927	UVM_INFO @ 1353549781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	46172341309182513231660588349054640464853056391500178356246982220061801263484	2660	UVM_INFO @ 756612819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	23353161194139943704095184396148898096194717248464476910099548595153697702050	1618	UVM_INFO @ 1174786526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	12694736272064262923978267443074437358123875435059272611020370419547829742852	4592	UVM_INFO @ 494054872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	69966702441892271617907204867668892056103382235479422223899151242405142561960	4540	UVM_INFO @ 584989660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	78506221683867594698061572242615525705665223073001725807886003566902020443197	8464	UVM_INFO @ 48710435674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	9609868398748363665855332041233753207431880811926626961573878700513349085468	2475	UVM_INFO @ 3153698300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	83336359851798148773285658597599233473529240744250583251692244239672178036544	1651	UVM_INFO @ 2373206182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	105858151284310880291822386775080858950662056958444465096891752309576501587770	5607	UVM_INFO @ 477365063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	2753427148278058451272938743144724334110989401085544114123817368238519619731	4100	UVM_INFO @ 521081132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	81947389121436672885112273016080762813404608460602683432352068069637073884805	1417	UVM_INFO @ 489232198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	72339673665133999763012026075718811602138519986011270071531163288585884051136	1034	UVM_INFO @ 197924151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	34885965218569819234493444501951488901965892714074729708329646476259660827929	485	UVM_INFO @ 873405410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	71803965771358274189734968578803407156770038694090244546902892116793836995938	1718	UVM_INFO @ 182755702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	21001577119709105539531822144613555464400742567637217748743581283601727479691	1806	UVM_INFO @ 874111924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	48930229748571717909057423689609940476193785368114212340637718432282985604807	2564	UVM_INFO @ 747390491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	30365014776522833479967389294213290681147997699095774341503555291412788421504	729	UVM_INFO @ 335444054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	76095799801358746267253470494165599710370705522597297983243243324116261528027	295	UVM_INFO @ 154917645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	57007393605712621807685902774773253739995775449176755530457598421900218441858	1123	UVM_INFO @ 221297490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	69405609356608790318065944717481493705498946886873123753451168748062143814433	464	UVM_INFO @ 234369462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	43583047457349379308955347493806226565700690314759331632039179018180652033441	2374	UVM_INFO @ 738451838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	20083325208424360108126448842817954556118582722603452933515491094041016384298	1456	UVM_INFO @ 115460152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	65868408474111887429179294945590483908820869779532679329498546904409841047447	4709	UVM_INFO @ 302035807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	53420955862521194240911946191116465027277504982954248202956083107611926805088	1618	UVM_INFO @ 2460964201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	94649293631082420279278365264490189958111102040123090722855218832480698348800	4968	UVM_INFO @ 2003264320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	102898089244068502453599547942181038066282356253877997936526325245313700014198	2378	UVM_INFO @ 165835645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	51203347637734346506657456371951723551718299228335786201934297300306699277830	2544	UVM_INFO @ 1382524867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	81945221069615550327702528711858132042134146568542206338295213134235663909324	2012	UVM_INFO @ 2265252194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	72431932230436413758014859938001115482253496532377346257305446708059479359105	12134	UVM_INFO @ 460298696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	94724891767723664818571788474468732344262812174927296133270158926161152092484	4004	UVM_INFO @ 1560655455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	73394896005426116214248593314961113354175156024711287184034751561009378362096	3462	UVM_INFO @ 331097737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	38442444495764192410322609758948694345979679516117728772348167855423607804879	5398	UVM_INFO @ 124442666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	65509412327907285368841210511007192526709300278687777770039315727505259397574	4027	UVM_INFO @ 180393667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	115095486437193159721689518726368436970583351323641096916813136017377262496108	661	UVM_INFO @ 144914491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	38406851880994534263059958012920211407210675525997744751079602708716167389460	5671	UVM_INFO @ 6142295744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_				30 test runs
	otp_ctrl_check_fail	107999816011244499493528260354234450334006576426300723837361670762095239560861	2322	UVM_INFO @ 450217548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	2645748793671252005372064272981681707595561204946341131873847398213526614477	4156	UVM_INFO @ 254388858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	41830807911699585401247245265292852258681218486398783851649663325981864610343	3253	UVM_INFO @ 647987051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	96740102072874214266343804274251109598431652448618259475046631783399609528454	1030	UVM_INFO @ 200304767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	5421140649698745640595650858822324761945900705601919603059657513524124356346	7421	UVM_INFO @ 1575076550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	15472072108682564390205816926340983863960463085534932865623718521540319278623	5234	UVM_INFO @ 424032747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	79896938857460503881724944667724977329760837347224680240314861792013285006509	4488	UVM_INFO @ 3217257460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	93207895461180535303691249281929097641748231957032673327854199952253523469321	3847	UVM_INFO @ 488345437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	80075508842274634204347826570922903342335666128235525956015073457797588642187	195	UVM_INFO @ 79465654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	79915859216358121342715923978535322504575705901329492497121924530218770405673	2204	UVM_INFO @ 2854593015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	44979190991180525661337201746260845140337239338908212205905472610988123874001	6167	UVM_INFO @ 686263392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	78128265429746058878928467460564796829432211861845201071917992512189195846483	15313	UVM_INFO @ 2205344605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	74743874480310051264691984052676573812136811031273126857870430565357466640121	2076	UVM_INFO @ 5121050429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	48096469711352059742681676123525122620762046054696216384045599492334046098347	8662	UVM_INFO @ 2052174401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	10692241744843163919521951124408724878732660830870640463737831723213694428009	8150	UVM_INFO @ 1698707623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	73076577012675472684076893510966727090513845661834922582860322718385436561434	337	UVM_INFO @ 97159445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	95426588253799411066147040791517038750583108384926062633518096668602003792399	13260	UVM_INFO @ 1425675857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	73230238988381614469564442411214960721332819446763276814214707412216544501330	561	UVM_INFO @ 85060606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	45105582989862662852868771956697942971055584842458777905231264359636530568983	543	UVM_INFO @ 313215502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	112928786205836102357834450674693938331335539285305458020554398219161789737910	3676	UVM_INFO @ 263107204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	29583753486781929854438028933033466253703838981908978000695965733897146587879	1381	UVM_INFO @ 573235228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	15545380288539293545556407103227795166153050096656847606651296837826041746960	485	UVM_INFO @ 280331056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	14854199821332290689688106996222016741412659703780422873303065382731734543257	5335	UVM_INFO @ 569318130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	21231394394746796345185095309142187486478530180015650294153561258824742757832	1957	UVM_INFO @ 1264116374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	68909210600949809879873834300942486809045844802219514420043229571516426099371	1550	UVM_INFO @ 15951561880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	64323518722313756918504519726039081559240492792024883645801412651892726536405	6959	UVM_INFO @ 4550289083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	51782850742614385506465358018086163541045185043911509823284684344586877955643	3811	UVM_INFO @ 30106431247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	36037122153344314120696730095268442672366673369918875134659878915255197757062	2787	UVM_INFO @ 6183879516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	100834197418186994715234558158253563474853337143866370994839358387532334718056	165	UVM_INFO @ 47287840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	43476484441989295606280019494142391652595434571006527051309130154535893526361	3329	UVM_INFO @ 748236008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!				28 test runs
	otp_ctrl_init_fail	31202231012308275530975191760471828181294028368711416323770158375887543981149	1339	UVM_INFO @ 2076072498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	60495469782930748805697101018948775536943124017106018038178431161214830052846	1621	UVM_INFO @ 313670466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	95172055806546616478775847115363836751798429936291512605561747083227618557317	1223	UVM_INFO @ 303984705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	87711868648911003188373415992018261467497125817769318723869046054360827374687	909	UVM_INFO @ 1683346630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	23810223244020130161236699607520104486428246704337933971450288940701456460878	1525	UVM_INFO @ 558888904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	7907492833807942320530983191982917699247818625675527044507002187393343631758	1231	UVM_INFO @ 452129190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	8818672051131547222271010507021279424651917635110576951124367276127139672266	3479	UVM_INFO @ 1423311564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	83641141832849118455345131072441542450600866800673538744291178264709072601334	1253	UVM_INFO @ 525796946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	78787615765386885459294033202401710864890572842936878169586608171050724595932	1655	UVM_INFO @ 2207544537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	60084468559783418051848450250113464795132289659929625544459179495013881785706	801	UVM_INFO @ 1861673408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	24443383846963443450317028737918089998304452690336600646811990382585837231802	1405	UVM_INFO @ 488125287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	21393948133440327386519440580316068071175558525901838414846203864322996687392	1449	UVM_INFO @ 245516676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	111360943721127955554790616906808825623150928482015224698702161734621076083465	1647	UVM_INFO @ 281688734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	12802410866586534674340204871956680698636357641028344881531135588601105400808	1713	UVM_INFO @ 2247885515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	101949643226080295649420933484402111385441262410232113710782650795545963562043	1737	UVM_INFO @ 2345218064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	22167619545856899226702917791395085563570451871080444347657911716513737503153	2543	UVM_INFO @ 180933502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	66604542285345134064689669351712828290330028757842111752020877079101627399216	3313	UVM_INFO @ 1640977325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	13133116117255324640523504395432797405080278151181151111899588351549889634846	1465	UVM_INFO @ 244327386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	11047233135949517583435185070056064852203998472595301966595790716690149223004	1529	UVM_INFO @ 270311864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	105196307876613118235098509352149901851638610113142923875153522696529484917683	1735	UVM_INFO @ 112559217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	97469293396290547314624906618300062637929823292230206243764296987450049987731	1513	UVM_INFO @ 288936717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	110967980061724924892784831533545824329431675521638016241094559642845394650866	2637	UVM_INFO @ 213140888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	87612583717884492278139077057007997304903304181211954105836166926624106632058	1651	UVM_INFO @ 303658375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	74435477376470739300740007176264225559800019472874627247090184992060816666276	1757	UVM_INFO @ 2253583641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	10237514480573054640986776410352358859556611972890467277831674721065331181860	1959	UVM_INFO @ 1207102030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	64566594688158331443762377378423821715217000054207128271095089816883409258965	2635	UVM_INFO @ 1158938886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	74036386849016262038095438909017234560213471187753176519410543566307001233784	1317	UVM_INFO @ 2005828337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	8946030977370736319356443073166004892187872781607071209611402023688795900600	1411	UVM_INFO @ 1283107437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.intr_state				22 test runs
	otp_ctrl_stress_all_with_rand_reset	84653683780836848267788693170623888756508913995374353150121359027078429730898	6845	UVM_INFO @ 2027599182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	20756315816715453417849574796551883791558817339132937656817399735791778187446	171	UVM_INFO @ 37807787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	85692465504525981262061471906882054920283358900951703467066440360546042954673	4987	UVM_INFO @ 1496068557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	63944292315065163030183757802458364113920545592238551241744253827882633994321	431	UVM_INFO @ 1361088776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	36429953909608819747655744334578846341048251853892961868472683616363395336543	1510	UVM_INFO @ 1043476112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	32119594466570293020101291195239565733750126847450009180715454854388909788788	1354	UVM_INFO @ 338177295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	106569140321288244224116725051516085331635622886136546501679893380326574953128	406	UVM_INFO @ 11730017125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	37580953783199207673058466576276030650793584304028120108526023499509579581346	23291	UVM_INFO @ 2408830310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	55813641485099914512714857314224465005100280217484934430222725499207481567400	10435	UVM_INFO @ 5628134064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	48869996894708701188246416457009109768867902344353314239127916325477781491896	9571	UVM_INFO @ 12493673997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	18084924828053644999493628039567261622821289136530219646120319169571372946019	193	UVM_INFO @ 34821564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	61287495339922387622085671298669119386340890163688076758296455299257529282318	13005	UVM_INFO @ 2875604172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	81942537741679791363337979454141168652777902264325459748448528492347342148819	5036	UVM_INFO @ 3392896344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	101413744564823373489262939575454187609439999365129622654319538844942914899290	361	UVM_INFO @ 75802017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	23941430855811195827606386925165096807627828124727818023635144859520616117415	1205	UVM_INFO @ 293271929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	107263602135733418871008931262848326465161000504346013243006605635179482521994	424	UVM_INFO @ 579688558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	92227818353625620228191032986494670775392088734031571542045517629862495037397	157	UVM_INFO @ 82054483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	60881304879936634860989685953968274532333678317492001653109715667843482341744	7593	UVM_INFO @ 2913394198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	20384524664494934883498955380127813989542330896514048104894899286320171295460	4557	UVM_INFO @ 14642375896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	79341069792027612639092809584111897491232765177405551308813276769371202631908	15273	UVM_INFO @ 1453385321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	99711688528282413169952995045559315818732356118776704463307620116653665016993	8876	UVM_INFO @ 1755119453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	56027613605474471940895218605688893988710142236013597860195028180023645767695	5087	UVM_INFO @ 1122304830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error				21 test runs
	otp_ctrl_dai_errs	38791952545172013011616505857173244680658241671089710142254818332166467135404	2176	UVM_INFO @ 129735446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	53083724167000890375439040032167120932798847643723094201513962826776176951858	15756	UVM_INFO @ 3113881693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	19876251426495579122295989002275190127273965596306166444716921792967464750328	4945	UVM_INFO @ 220173067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	2750392059489950080846769885226931263110161613288263876573835336808556377188	72994	UVM_INFO @ 50155179185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	110230111643561753136768125253124311271105878497490861346762680160881825833107	654	UVM_INFO @ 97287206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	72361606626974928472499596019314831736659005017749476924878860719357667731012	18543	UVM_INFO @ 18874274700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	18140916004123131465376353514044932244274949480983758975801234339667377848717	342	UVM_INFO @ 90019982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	45373614750314251423329055610119811306088361177875284587283921018137125098705	4593	UVM_INFO @ 700766029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	96867436208019282994085413049671634374555102632230705533224032779669295444538	1411	UVM_INFO @ 848498594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	49942870707143800567924298997732721347342921737318372782457159220291404955102	2585	UVM_INFO @ 214212800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	23781931103586154383342545422631517985485165543804611661634413982008235722221	6237	UVM_INFO @ 604895374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	46412890386052214145713340243641602441982609773099395266590809353239441555975	3683	UVM_INFO @ 515732124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	102272496678603479850570701580496634075174916415714274399466938928176126255753	617	UVM_INFO @ 161848729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	46038046558931458913747918360467819689460226755315213198014952249999599571187	2323	UVM_INFO @ 777243321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	106554310765598085024746478586717549969806759794847135282299741549788141472193	1729	UVM_INFO @ 1992567319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	86614558211972051664624644813017964680829724227621061817219980169224287075565	2943	UVM_INFO @ 472283592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	50894128243007237551732276531703333658681681826862056919352365910195197584486	762	UVM_INFO @ 167482977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	2986571197092844789065485714313121524408585077244378571125629841533763362824	7771	UVM_INFO @ 4471963596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	99854925858097746170307363425592427598218177625724897614537766710685334580768	5900	UVM_INFO @ 138367981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9151515660399331949289146413573339086753891618107855416408579886381393689305	33237	UVM_INFO @ 10551276328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	54765304064761119783290866230210090070839304900834704412170648583639328319173	4363	UVM_INFO @ 3586182639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_check_error has unexpected timeout error				21 test runs
	otp_ctrl_dai_errs	74833584515820071167548447285174222821984563173859488895102582745566887025591	5063	UVM_INFO @ 264074424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	105561319408507872087733422983947441145525301815072947172754458335084948103969	2142	UVM_INFO @ 215161243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	105089266741056717272818722930546581189264060045034114677125882199981437676521	12165	UVM_INFO @ 3544982359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	21213364593299205856439494152954657111491238785312352228360095849527648095445	1992	UVM_INFO @ 511417529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	79665164440443519749465871584460499675971148807951432205534743381532178674207	1575	UVM_INFO @ 2557778638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	79546745983187249761414892899827052025890077774310845042249936694278536721884	396	UVM_INFO @ 194318243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	79092604597201110874159032848094015914888485990667452793368642217686863208587	2810	UVM_INFO @ 438234237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	24862133503212710500442201681214775486304493268060399627840512740745510360613	5327	UVM_INFO @ 1047927750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	35594330072889317693350398762436151581932369988771193309534226965659254814056	2266	UVM_INFO @ 2481517828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	51028509164595323505480579901711848229809736444585769070241193924565492808620	5797	UVM_INFO @ 1725464318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	55466550269516264842424268308340188237383082226576936772663741678256261234771	449	UVM_INFO @ 861563221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	112462567784883190432822911607516042807144458839802990017993653586198331997144	2060	UVM_INFO @ 2535911804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	1072607940381738217249761997145472087398292509941267103474928373324365753032	1061	UVM_INFO @ 1532432362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	61625892124233082313782320562093479758913108043809693779237650067988872980585	2218	UVM_INFO @ 2810218727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	19499558191343687074361714464393374354517376205940063589639338949938014239921	4836	UVM_INFO @ 1688910228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	71147026531500140485181047007382729659488857515457800663527646982213117881176	4337	UVM_INFO @ 1114111395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	36873039173344317606823690406867390592782838434719671558149504763751649879374	581	UVM_INFO @ 1296303267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	13272580219052767778857928007813615150544821676382147692211783145221854459102	4200	UVM_INFO @ 377771372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	66859153622683325075764877375635326643501138034311248505331965049570898917553	11156	UVM_INFO @ 436850054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	5646400352060169005401135780819280437443600166317114769686719032164389815765	8740	UVM_INFO @ 619295164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	92292132624222022218427277102258805583384264441491769941430282060981392089078	866	UVM_INFO @ 337606414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1824) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				20 test runs
	otp_ctrl_csr_mem_rw_with_rand_reset	69122405952749734386429700327683803314945733427252804105650461130960747172869	104	UVM_INFO @ 116574146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	18042842636550252795669868029924733200260376700963146126184541632137849608070	439	UVM_INFO @ 3701606846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	91298385248343866878020888197192201644904192139075209878798950079544092498847	3230	UVM_INFO @ 1597022463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	13403475246057348990785215499055048339127549667109976048849697637879556961002	98	UVM_INFO @ 28774888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	21334501535291381563978415575240145125853283026598382524124528555624061195155	1375	UVM_INFO @ 301863883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	1123470455802150087152720951069510571945026386322966105061858716533414445286	98	UVM_INFO @ 103539848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	49445936092434763611052833426151171239913199545644390941684795714341651798965	43068	UVM_INFO @ 2027461880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	14218615503263792040607082454734140308083522263169958449624635361890414445472	40621	UVM_INFO @ 9334300648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	59058551131949281687592415434042121423274732043775146260094001493268801229581	652	UVM_INFO @ 465738584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	109879058089287530319102682161052903961637625133363985006294052290014216695888	98	UVM_INFO @ 27828626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	101330940783704088533188012381566462276801348888170052315131431397921201241860	98	UVM_INFO @ 431099488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	98598507531446805064140776125680133302950299379990691059998000925989448807640	2256	UVM_INFO @ 157061815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	87945269433420019265145809417092848321617315013166813986134312797297095756130	1340	UVM_INFO @ 218646591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	50046946710623363284475322452707140905199251645662226572109439239782262269814	150	UVM_INFO @ 5352485365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9687059217318740759241828095280591524883804981075877541949296307669013557455	14711	UVM_INFO @ 26855952234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	113357462289244628352096547743056141723262482022503333576603012414722005341092	2330	UVM_INFO @ 786206573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	51874357121765730670315103669541777402256282054424477719250435060705547432149	98	UVM_INFO @ 28506572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	89155488320641490555640142593394373616563276308546325818694304833019751005632	482	UVM_INFO @ 17143213524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	88446092114048450757176400404825319900810318854072513399931519996774618867295	98	UVM_INFO @ 28215037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	20315917578023053443026515121394880548001151708598759630309770334254740217331	4382	UVM_INFO @ 9831719700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_macro_error does not trigger!				15 test runs
	otp_ctrl_init_fail	41661411121957026234609955677562955290883230881638116966086629134234879952295	1379	UVM_INFO @ 308310202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	38146246108430232060891696402337321101870555925367370152051743254142637081083	1183	UVM_INFO @ 1565988203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	48531096307033371420356327249073078530956492226174556541218504613478128102417	1127	UVM_INFO @ 232402593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	87086194493592555916931685074175014442542129438201685922674632666434884712620	2191	UVM_INFO @ 168842531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	24380035736653315220801595778035612590683335512102116913567801580694696397973	1481	UVM_INFO @ 2076742366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	86533666090528283615403974811445326442269199860629382343965405117812133587956	1907	UVM_INFO @ 1478739282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	24170005882125472941215159546792303562253884738268357185503310563676189711857	1711	UVM_INFO @ 940337929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	42742154513543582451415223350683221272403366373171591787952423001745949925393	1783	UVM_INFO @ 320382437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	110344802072705433025631891220364413761122266058042343605587356078211580995090	1045	UVM_INFO @ 475258273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	48996989142481065787498047696279953521425599175274783799223259261767653110734	1387	UVM_INFO @ 1970527409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	92731727234594711508502389190031656091648996371231470503569807284776235709001	2253	UVM_INFO @ 225171901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	81651687409701996162035889494246049060796722777808906327176855070554797758748	1989	UVM_INFO @ 286590432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	56497947329094611942231409965541467635724887869753227558146984310296511824256	951	UVM_INFO @ 438772658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	62692573635805954755856261742654696315093951981288731483902254578474290768042	2345	UVM_INFO @ 1245718997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	75615005275836761260292761613841335456233838974950690732897135809060180559652	1537	UVM_INFO @ 273086123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles				11 test runs
	otp_ctrl_stress_all	114526616049660366666684445346830124318966616548643332466674186308037816026838	4338	UVM_INFO @ 6656466827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	27874838396384492574115581606041229285819320958315873934643812229493681349058	918	UVM_INFO @ 90015676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	6359480643940307358705127756045861044906457754184365221244614176975733921871	46507	UVM_INFO @ 5296522709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	20467249816128279063945112906611691700821632832861021100418888448785347931502	5909	UVM_INFO @ 857897232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	40483151586830023990910296286607905389393565412550283892441433748388294109458	1333	UVM_INFO @ 52708242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	99437828612909649999242045765283273014329189099021742534165953816567889250396	1972	UVM_INFO @ 819255219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	55472324979663859941331062953695650605770892957846890512111319280020656202183	5453	UVM_INFO @ 13544913736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	6744430040986072004476496190932748485987964055972631997080076957795807460535	5957	UVM_INFO @ 2286490174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	85214426033766124167875892746335361369943812407856190223282632534249066337806	15899	UVM_INFO @ 4949794494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	44855105550489076136195171390023419947115987030737777187342988539281025336987	3039	UVM_INFO @ 248664720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	59005442713071793006115439017786680312292780409978461567477358687921533483196	22976	UVM_INFO @ 3087654278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:841) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				7 test runs
	otp_ctrl_stress_all_with_rand_reset	96616997967047534364200306709455814503360500391196671545383558467744861932791	28071	UVM_INFO @ 39633768397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_csr_mem_rw_with_rand_reset	102584130129272524797490344911442034514328099992161518735524614427439760587485	98	UVM_INFO @ 29871467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	30595299136774119641896724311769093580033043258004295846255794585423415383703	98	UVM_INFO @ 433561306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	43863623673041786751171730212192274845489411721495166925673173803590246321341	1138	UVM_INFO @ 69277903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	262870976654584413050466612984609626045739323106139812702957805318651051433	2843	UVM_INFO @ 1189022690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	85307375977342444228088300199408738393643768788298660830108686172509653219486	1941	UVM_INFO @ 1233264333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	3251877496214927478650623124118905082248066537445966649175829856866971655295	8291	UVM_INFO @ 1094797763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!				5 test runs
	otp_ctrl_background_chks	90217894006884849055894919759804651980654866590302702958963475240244260117215	5518	UVM_INFO @ 1710157089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	75009470566516187878701385442013019237692726158490539811151848651540861400069	17048	UVM_INFO @ 6648076115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	114702962073438819558832766734745062410753361663471799132442468900330167719352	28936	UVM_INFO @ 52925148077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	78043125733051254450185365953470349265691439463791259702246401086087197676386	1655	UVM_INFO @ 6418276671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	101234665688591953278200300170360870211107365053090431921901130933515518164383	6378	UVM_INFO @ 1449122692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles.				3 test runs
	otp_ctrl_sec_cm	96221445238160999761681425610333652866795161786102386024206935839387271933436	922	UVM_INFO @ 12154364175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_tl_intg_err	71205687288264469195439510983212189151237704548569446066015627814231429109264	168	UVM_INFO @ 4522623129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_tl_intg_err	104948591117938434553281026855698618660936079886356438118112242131602883829372	175	UVM_INFO @ 4134043663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_prim_otp_alert) did not fire in * cycles.				3 test runs
	otp_ctrl_tl_intg_err	69068872656155708479804902714194285069681721288433186749395628619241630336829	225	UVM_INFO @ 971391794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_tl_intg_err	77397692793692474450649264783814928451284350154944403509120893013689144986809	121	UVM_INFO @ 1952278278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_tl_intg_err	110459740909355642309828939409530322372052134712154087528273790202130126036166	111	UVM_INFO @ 240813697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr rdata* readout mismatch				2 test runs
	otp_ctrl_stress_all_with_rand_reset	95880790347104543088958054220562122670649351976081334371807326329814927122784	99	UVM_INFO @ 1974209165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	92102664200652193082901599488387336704155147511530987987119548428771809939659	401	UVM_INFO @ 4249431646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)'				2 test runs
	otp_ctrl_stress_all_with_rand_reset	70150508540504839112148003087438785342949619120225409566161211078419737701172	307	UVM_ERROR @ 71263656 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A UVM_INFO @ 71263656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	113927780439426575751117819774004283904352960688965409179858909596407756028237	189	UVM_ERROR @ 2754153575 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A UVM_INFO @ 2754153575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred!				2 test runs
	otp_ctrl_stress_all_with_rand_reset	89909061580270208113171396384136155411218918032018737738251661131978038978245	112	UVM_INFO @ 10033121094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	112882806520180647794736361048853399889844012889874239177840247792462890330460	12735	UVM_INFO @ 12284668814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr c rdata* readout mismatch				1 test run
	otp_ctrl_stress_all_with_rand_reset	21130268382316806985218882335144395565820376594315582663305533794550302312662	3243	UVM_INFO @ 18614843578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen				1 test run
	otp_ctrl_stress_all_with_rand_reset	55428355485909487973036996935133526479215336044966371689957719300487548091354	2379	UVM_INFO @ 2434335694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed				1 test run
	otp_ctrl_stress_all_with_rand_reset	17945014510032273744395137487306735982427058540150181892400691621197529733938	12794	UVM_INFO @ 4341416881 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 4342316881 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 4342516881 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 4343276881 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1