Simulation Results: pwrmgr

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 97.57 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.38 %
  • cond
  • 96.75 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
94.16%
V2S
100.00%
V3
65.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.790s 26.604us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.830s 111.797us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.810s 43.462us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.840s 443.230us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.800s 43.640us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.990s 84.530us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.810s 43.462us 5 5 100.00
pwrmgr_csr_aliasing 0.800s 43.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.090s 243.434us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.090s 243.434us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 0.970s 43.600us 10 10 100.00
pwrmgr_lowpower_invalid 0.860s 49.680us 10 10 100.00
reset 16 20 80.00
pwrmgr_reset 2.280s 1000.000us 8 10 80.00
pwrmgr_reset_invalid 0.990s 104.110us 8 10 80.00
main_power_glitch_reset 8 10 80.00
pwrmgr_reset 2.280s 1000.000us 8 10 80.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.150s 323.484us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.110s 246.563us 10 10 100.00
disable_rom_integrity_check 9 10 90.00
pwrmgr_disable_rom_integrity_check 1.460s 1000.000us 9 10 90.00
stress_all 7 10 70.00
pwrmgr_stress_all 38.010s 10429.667us 7 10 70.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.790s 132.955us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.140s 266.083us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.140s 266.083us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.830s 111.797us 1 1 100.00
pwrmgr_csr_rw 0.810s 43.462us 5 5 100.00
pwrmgr_csr_aliasing 0.800s 43.640us 1 1 100.00
pwrmgr_same_csr_outstanding 1.000s 51.178us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.830s 111.797us 1 1 100.00
pwrmgr_csr_rw 0.810s 43.462us 5 5 100.00
pwrmgr_csr_aliasing 0.800s 43.640us 1 1 100.00
pwrmgr_same_csr_outstanding 1.000s 51.178us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 1.950s 206.770us 25 25 100.00
pwrmgr_sec_cm 1.530s 1029.187us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.530s 1029.187us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.530s 1029.187us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 1.950s 206.770us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.620s 735.226us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.150s 323.484us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.290s 814.464us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.060s 54.378us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.790s 51.219us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.530s 1029.187us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.530s 1029.187us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.530s 1029.187us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.750s 35.047us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.730s 62.293us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.190s 98.454us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.810s 43.462us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.810s 43.462us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 4 10 40.00
pwrmgr_escalation_timeout 0.980s 101.668us 4 10 40.00
stress_all_with_rand_reset 9 10 90.00
pwrmgr_stress_all_with_rand_reset 9.100s 3721.453us 9 10 90.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 6 test runs
pwrmgr_escalation_timeout 11573325677843964464199628276302335940625108314292513723979671940842378437395 85
UVM_ERROR @ 384547845 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 384547845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 79072792594654733905990465345175589856675878470184361529608187388663488928200 85
UVM_ERROR @ 101668468 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 101668468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 16214707547339541519123292686014590888857683571178006745727657354376622584679 85
UVM_ERROR @ 145640736 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 145640736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 10337406359711283737229557320026614977140393497920610628388497753083185843925 85
UVM_ERROR @ 370321912 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 370321912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 19248132820684180557522499561622996156811439151614294813474393314209839412617 85
UVM_ERROR @ 627414702 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 627414702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 44960394630416599824835843753086713297490446855268556086244860933523968063853 85
UVM_ERROR @ 330167493 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 330167493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 3 test runs
pwrmgr_stress_all 763726692298074460335013840380379091749308782584309453124193141512048301542 602
UVM_INFO @ 11831088206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 43434102417476506769469883419234406359351941642815741489185375662431428118044 372
UVM_INFO @ 10656325404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 79843881309677602137665483409552119059557185311446520808987262618502987526142 316
UVM_INFO @ 10429666897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
pwrmgr_reset 3213183009133055248700140259035739812002312003896535541716588573828508368442 144
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 76571404625921280926486460789457765008538746669176150787492299082495996089413 97
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 38572284212782439536015205506606397511562869982545276768130504080114909542807 103
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitAckPwrUp 1 test run
pwrmgr_reset_invalid 5029780845711773366417789721745545692108666430775267828639883260358624097007 174
UVM_INFO @ 89709398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks 1 test run
pwrmgr_reset_invalid 46412942064507729988837614658888518903743429279938803884775103430532261116419 96
UVM_INFO @ 26840752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1209) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
pwrmgr_stress_all_with_rand_reset 88594170333274664770403454583598820978334490563080281431548256877729720115597 106
UVM_INFO @ 124900395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---