Simulation Results

Simulation Results: rom_ctrl/192kb

19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.41 %

code
98.50 %

assert
97.68 %

func
99.04 %

line
99.21 %

branch
99.28 %

cond
98.66 %

toggle
95.34 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.77%
V2S		96.61%
V3		90.00%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	23.720s	1608.781us	2	2	100.00
csr_hw_reset				1	1	100.00
	rom_ctrl_csr_hw_reset	32.490s	102.598us	1	1	100.00
csr_rw				5	5	100.00
	rom_ctrl_csr_rw	17.300s	52.884us	5	5	100.00
csr_bit_bash				1	1	100.00
	rom_ctrl_csr_bit_bash	14.320s	111.655us	1	1	100.00
csr_aliasing				1	1	100.00
	rom_ctrl_csr_aliasing	10.800s	107.285us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	17.700s	56.561us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rom_ctrl_csr_rw	17.300s	52.884us	5	5	100.00
	rom_ctrl_csr_aliasing	10.800s	107.285us	1	1	100.00
mem_walk				1	1	100.00
	rom_ctrl_mem_walk	11.530s	61.683us	1	1	100.00
mem_partial_access				1	1	100.00
	rom_ctrl_mem_partial_access	10.940s	56.224us	1	1	100.00

68/71 passed

95.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				0	2	0.00
	rom_ctrl_max_throughput_chk	20.350s	4087.191us	0	2	0.00
stress_all				19	20	95.00
	rom_ctrl_stress_all	10800.139s	0.000us	19	20	95.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	21.950s	57.647us	2	2	100.00
alert_test				10	10	100.00
	rom_ctrl_alert_test	18.260s	51.483us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rom_ctrl_tl_errors	32.830s	2185.244us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rom_ctrl_tl_errors	32.830s	2185.244us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rom_ctrl_csr_hw_reset	32.490s	102.598us	1	1	100.00
	rom_ctrl_csr_rw	17.300s	52.884us	5	5	100.00
	rom_ctrl_csr_aliasing	10.800s	107.285us	1	1	100.00
	rom_ctrl_same_csr_outstanding	22.720s	78.709us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rom_ctrl_csr_hw_reset	32.490s	102.598us	1	1	100.00
	rom_ctrl_csr_rw	17.300s	52.884us	5	5	100.00
	rom_ctrl_csr_aliasing	10.800s	107.285us	1	1	100.00
	rom_ctrl_same_csr_outstanding	22.720s	78.709us	5	5	100.00

V2S

57/59 passed

96.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
passthru_mem_tl_intg_err				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	170.380s	12403.014us	5	5	100.00
tl_intg_err				30	30	100.00
	rom_ctrl_sec_cm	2358.600s	1009.538us	5	5	100.00
	rom_ctrl_tl_intg_err	503.640s	207.162us	25	25	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	2358.600s	1009.538us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	2358.600s	1009.538us	5	5	100.00
sec_cm_checker_ctr_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
sec_cm_checker_ctrl_flow_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
sec_cm_checker_fsm_local_esc				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
sec_cm_compare_ctrl_flow_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
sec_cm_compare_ctr_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	2358.600s	1009.538us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	2358.600s	1009.538us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	23.720s	1608.781us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	23.720s	1608.781us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	23.720s	1608.781us	2	2	100.00
sec_cm_bus_integrity				25	25	100.00
	rom_ctrl_tl_intg_err	503.640s	207.162us	25	25	100.00
sec_cm_bus_local_esc				20	22	90.91
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
	rom_ctrl_kmac_err_chk	21.950s	57.647us	2	2	100.00
sec_cm_mux_mubi				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
sec_cm_mux_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
sec_cm_ctrl_redun				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	754.840s	26553.719us	18	20	90.00
sec_cm_ctrl_mem_integrity				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	170.380s	12403.014us	5	5	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	2358.600s	1009.538us	5	5	100.00

18/20 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				18	20	90.00
	rom_ctrl_stress_all_with_rand_reset	287.550s	17549.384us	18	20	90.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [] vs [*])				2 test runs
	rom_ctrl_max_throughput_chk	83964155039193493375161676427419374970732164489269364362210802331496247548160	85	UVM_INFO @ 4087190724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_max_throughput_chk	30988243168818711809269732487654222218194207435938374510447412136110735834934	85	UVM_INFO @ 2671212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:474) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *)				2 test runs
	rom_ctrl_stress_all_with_rand_reset	100468033327928033251062193272551478930765195395533615007336661349598942683523	86	UVM_INFO @ 1399677935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	108215579467493851004327704951110574893011100784331970499432494568865701463086	88	UVM_INFO @ 435114834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rom_ctrl_corrupt_sig_fatal_chk	27138756851220355731834512851507903424895015434308146188334907671061850547024	113	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	18777159203358588073581418546098173771258077077570825952622883760457368152137	105	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rom_ctrl_stress_all	94261802528521067055077908975665747555982899437157178402736712627843411662404	None