Simulation Results: rram_ctrl

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 63.21 %
  • code
  • 54.45 %
  • assert
  • 79.77 %
  • func
  • 55.41 %
  • block
  • 87.47 %
  • line
  • 89.32 %
  • branch
  • 72.72 %
  • toggle
  • 39.07 %
  • FSM
  • 16.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rram_ctrl_smoke 8.000s 222.613us 1 1 100.00
csr_hw_reset 1 1 100.00
rram_ctrl_csr_hw_reset 13.000s 308.019us 1 1 100.00
csr_rw 5 5 100.00
rram_ctrl_csr_rw 11.000s 167.263us 5 5 100.00
csr_bit_bash 1 1 100.00
rram_ctrl_csr_bit_bash 39.000s 2577.913us 1 1 100.00
csr_aliasing 1 1 100.00
rram_ctrl_csr_aliasing 5.000s 166.907us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rram_ctrl_csr_mem_rw_with_rand_reset 9.000s 880.042us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rram_ctrl_csr_rw 11.000s 167.263us 5 5 100.00
rram_ctrl_csr_aliasing 5.000s 166.907us 1 1 100.00
mem_walk 1 1 100.00
rram_ctrl_mem_walk 5.000s 513.644us 1 1 100.00
mem_partial_access 1 1 100.00
rram_ctrl_mem_partial_access 9.000s 1530.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
rram_ctrl_intr_test 11.000s 2825.659us 10 10 100.00
alert_test 10 10 100.00
rram_ctrl_alert_test 11.000s 572.051us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rram_ctrl_tl_errors 13.000s 4276.139us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rram_ctrl_tl_errors 13.000s 4276.139us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rram_ctrl_csr_hw_reset 13.000s 308.019us 1 1 100.00
rram_ctrl_csr_rw 11.000s 167.263us 5 5 100.00
rram_ctrl_csr_aliasing 5.000s 166.907us 1 1 100.00
rram_ctrl_same_csr_outstanding 8.000s 137.270us 5 5 100.00
tl_d_partial_access 12 12 100.00
rram_ctrl_csr_hw_reset 13.000s 308.019us 1 1 100.00
rram_ctrl_csr_rw 11.000s 167.263us 5 5 100.00
rram_ctrl_csr_aliasing 5.000s 166.907us 1 1 100.00
rram_ctrl_same_csr_outstanding 8.000s 137.270us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 25 0.00
rram_ctrl_tl_intg_err 10.000s 680.996us 0 25 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 2 0.00
rram_ctrl_stress_all_with_rand_reset 8.000s 104.489us 0 1 0.00
rram_ctrl_stress_all 11.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq__tl_errors.svh:476) [rram_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_fault) is not inside '{"recov_err", "fatal_std_err", "fatal_err", "fatal_macro_err", "recov_macro_err"} 25 test runs
rram_ctrl_tl_intg_err 4279153175528941517992596881496658590236450064880991279320102763024950604298 90
UVM_INFO @ 221810169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 38358323495256004193399397956162437024464217866983745501295376055411125728370 97
UVM_INFO @ 213738669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 14347914322449307681898697153379003700391795880073011415862201282864593086036 90
UVM_INFO @ 103942970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 42726293615966000744661624127830825883686349928034782108361731728922148369402 94
UVM_INFO @ 247675342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 85633109651408155165776797064380651741507915272442711696450236901897468424929 90
UVM_INFO @ 680996418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 43541651600341434984821199693910929713485623589199495201824695957677753600088 90
UVM_INFO @ 119089857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 42488400718576243265806808858178951427526238394474528423756560561362066094918 90
UVM_INFO @ 111306415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 58651116492268348027345889135756487405804532816343274792758525091791489696112 94
UVM_INFO @ 760102430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 84882292072911986504234263894119493285367146570964285111829679266357582757952 90
UVM_INFO @ 111994448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 93138752347444275322391234137948153910693947168167487320853539512217330205356 94
UVM_INFO @ 306328559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 13665554808019952296461231904845736931793962777480124047022516629151870512416 94
UVM_INFO @ 434951753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 43741431955709906860765327846546465746863532941466592916270451569734279131520 97
UVM_INFO @ 445955239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 97685257781707568237120935453889458143891384078308160224811187124557383622112 94
UVM_INFO @ 530833453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 11136913299838196242156678021725760226836183482703734741756591599500865110947 90
UVM_INFO @ 277911151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 34213710165113792850422040789293216172783488872067476697340944437389805681423 97
UVM_INFO @ 112423185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 85343205012116363155981410491687312585849157831195585461058954502210728681663 97
UVM_INFO @ 221523309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 46733306140019123951574263099519661428374156571583171171481155751416874048815 97
UVM_INFO @ 150057876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 25887926201179072409547034048914638591323918987022638951137673109922956664426 94
UVM_INFO @ 205337236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 113543489588892447930023339014471689001245360857510905543092351040568002925414 94
UVM_INFO @ 135914965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 50645015782530892303398090864599207790270192970917380612523864938693766580707 90
UVM_INFO @ 154231647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 29743005287156846070255580172758914647101602453960200933935096052416037202823 97
UVM_INFO @ 132802411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 105802617630657653825759054382044888208567509244476124848473616890327519685341 97
UVM_INFO @ 394601538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 37861909158670509834002244408205683013933846732191805044070267002205712757598 94
UVM_INFO @ 413085172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 14728590633489830090157203987151610537393381120955583666371734068397537163590 97
UVM_INFO @ 107377708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rram_ctrl_tl_intg_err 81700000181714668431156218963053490156409518687879310419794202311761131674422 90
UVM_INFO @ 461305095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING [BDTYP] Cannot create an object of type 'rram_ctrl_stress_all_vseq' because it is not registered with the factory. 2 test runs
rram_ctrl_stress_all_with_rand_reset 86804180725020131807410592230266475619726160382046805684543984378015493089006 86
UVM_INFO @ 104489311 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
Instance Overrides:
rram_ctrl_stress_all 46458828017615188090903883966856861579376332895845409747930945275731235525415 85
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
Instance Overrides: