Simulation Results: rstmgr

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.78 %
  • code
  • 99.66 %
  • assert
  • 98.93 %
  • func
  • 97.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.31 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 2.270s 266.863us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.120s 99.533us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.190s 93.609us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 11.440s 2470.638us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.250s 112.158us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.640s 209.739us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.190s 93.609us 5 5 100.00
rstmgr_csr_aliasing 1.250s 112.158us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 1.360s 206.038us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 3.840s 570.491us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.490s 140.705us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 9.920s 2397.675us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 9.920s 2397.675us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 9.920s 2397.675us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 9.920s 2397.675us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 24.360s 3781.817us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.120s 78.247us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 4.630s 561.987us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 4.630s 561.987us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.120s 99.533us 1 1 100.00
rstmgr_csr_rw 1.190s 93.609us 5 5 100.00
rstmgr_csr_aliasing 1.250s 112.158us 1 1 100.00
rstmgr_same_csr_outstanding 2.130s 246.532us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.120s 99.533us 1 1 100.00
rstmgr_csr_rw 1.190s 93.609us 5 5 100.00
rstmgr_csr_aliasing 1.250s 112.158us 1 1 100.00
rstmgr_same_csr_outstanding 2.130s 246.532us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 44.300s 16822.296us 5 5 100.00
rstmgr_tl_intg_err 5.070s 1328.337us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 44.300s 16822.296us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 44.300s 16822.296us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 5.070s 1328.337us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.670s 209.983us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 25 25 100.00
rstmgr_leaf_rst_cnsty 14.510s 2807.341us 25 25 100.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 1.720s 301.528us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 44.300s 16822.296us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.190s 93.609us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.190s 93.609us 5 5 100.00