Simulation Results: rv_timer

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.50 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 99.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
52.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.260s 1122.674us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.750s 60.345us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 0.830s 15.691us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.310s 50.333us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.830s 16.397us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.260s 84.106us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 0.830s 15.691us 5 5 100.00
rv_timer_csr_aliasing 0.830s 16.397us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 10.040s 14607.609us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 3.900s 2438.724us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 406.050s 291347.831us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 406.050s 291347.831us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 13.160s 6611.771us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 0.850s 76.175us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 0.840s 18.411us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.290s 719.786us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.290s 719.786us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 0.750s 60.345us 1 1 100.00
rv_timer_csr_rw 0.830s 15.691us 5 5 100.00
rv_timer_csr_aliasing 0.830s 16.397us 1 1 100.00
rv_timer_same_csr_outstanding 1.020s 31.357us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 0.750s 60.345us 1 1 100.00
rv_timer_csr_rw 0.830s 15.691us 5 5 100.00
rv_timer_csr_aliasing 0.830s 16.397us 1 1 100.00
rv_timer_same_csr_outstanding 1.020s 31.357us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.280s 180.121us 5 5 100.00
rv_timer_tl_intg_err 1.510s 375.516us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 1.510s 375.516us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 10 10.00
rv_timer_min 2.010s 165.997us 1 10 10.00
max_value 0 10 0.00
rv_timer_max 1.290s 174.843us 0 10 0.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 44.430s 61912.944us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 10 test runs
rv_timer_max 35031101608318263005333784152149796812780339143172444627381932479041461719900 81
UVM_INFO @ 89442177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 38579496934956488818026069125167892627370872331693404192388486155016643642014 81
UVM_INFO @ 45332487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 22117783179094337944386657468034504802738744041516938175142602173677580407796 81
UVM_INFO @ 46694934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 82829341177122433722121778430058158914271256639453012653756576231562376909547 81
UVM_INFO @ 43954545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 66142491534901682225989113928910661590485594271171434025199903047845338340108 81
UVM_INFO @ 154718033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 85468747798836463431610261014021505297300139241091312931649124351681855886886 81
UVM_INFO @ 61530854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 79677034170659919960466599145246234616964710925355609279132550700765777468408 81
UVM_INFO @ 55876114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 40383869439062317621693715908422659391328164315566730352610024227998798979364 81
UVM_INFO @ 45990493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 45031685000004357977002057884590706907585044954469463126288894730079818646857 81
UVM_INFO @ 174842750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 38325454227197689261325457909583974657419944194149639407121683722437820544800 82
UVM_INFO @ 126105367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 9 test runs
rv_timer_min 40700282400526252779799030674829390497679938501703847450861661963341582643879 81
UVM_INFO @ 104638362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 99448155298138576817385468381456308762911693209033732343049509388325954731159 83
UVM_INFO @ 227311653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 97838930890952586208198279417818058741740689426689668172568445800658985977377 82
UVM_INFO @ 69051902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 115766361980697135989160203177764699586660825422013789036767675905104459815895 83
UVM_INFO @ 260501816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 88492106382528088225648098668500830114982326422619691070927353507355005405564 81
UVM_INFO @ 165997429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 29534467103198392133188703142712163881322494477805651512003978146401498216398 81
UVM_INFO @ 59815237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 9334366788274531085924081610525311806336543577292093093434814633851079447086 83
UVM_INFO @ 654283520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 66859117572828720100376874859493722298852843119238928944170257362182887245808 81
UVM_INFO @ 76092412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 7675405382713445052381811806553982173602085865994951498482923264308881582178 82
UVM_INFO @ 122829081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---