Simulation Results: spi_host

 
19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.58 %
  • code
  • 91.32 %
  • assert
  • 95.65 %
  • func
  • 90.76 %
  • block
  • 97.01 %
  • line
  • 98.76 %
  • branch
  • 93.45 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 78.000s 11014.372us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 66.755us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 30.292us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 1111.828us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 49.974us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 28.058us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 30.292us 5 5 100.00
spi_host_csr_aliasing 1.000s 49.974us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 16.321us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 50.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 27.160us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 23.000s 3837.983us 10 10 100.00
spi_host_error_cmd 2.000s 83.985us 10 10 100.00
spi_host_event 35.000s 2308.969us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 707.879us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 707.879us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 707.879us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 336.000s 8136.525us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 15.000s 525.811us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 77.918us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 707.879us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 707.879us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 78.000s 11014.372us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 78.000s 11014.372us 10 10 100.00
stress_all 9 10 90.00
spi_host_stress_all 2478.000s 1000000.000us 9 10 90.00
spien 10 10 100.00
spi_host_spien 28.000s 1397.403us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 1834.000s 591607.789us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 4.000s 143.466us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 23.000s 3837.983us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 23.657us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 18.509us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 5.000s 342.651us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 5.000s 342.651us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 66.755us 1 1 100.00
spi_host_csr_rw 2.000s 30.292us 5 5 100.00
spi_host_csr_aliasing 1.000s 49.974us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 25.652us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 66.755us 1 1 100.00
spi_host_csr_rw 2.000s 30.292us 5 5 100.00
spi_host_csr_aliasing 1.000s 49.974us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 25.652us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 180.256us 25 25 100.00
spi_host_sec_cm 2.000s 148.164us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 180.256us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_stress_all 26910741677725337277340503118816945520398687386654427843666050838938205454727 243
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---