Simulation Results

Simulation Results: adc_ctrl

08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
66.98 %

code
95.61 %

assert
91.73 %

func
13.61 %

line
98.83 %

branch
97.34 %

cond
87.55 %

toggle
99.76 %

FSM
94.59 %

Validation stages

V1		100.00%
V2		45.22%
V2S		100.00%
V3		0.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	21.250s	5932.126us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.410s	724.256us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	1.970s	535.112us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	108.690s	45586.190us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	4.900s	812.993us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.570s	499.333us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	1.970s	535.112us	5	5	100.00
	adc_ctrl_csr_aliasing	4.900s	812.993us	1	1	100.00

71/157 passed

45.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.640s	502.141us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.370s	458.002us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.200s	446.757us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.430s	508.185us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	2.210s	458.037us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.210s	407.630us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	2.020s	365.113us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.230s	462.156us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	16.000s	5261.755us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	101.290s	42066.135us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	274.820s	104631.579us	10	10	100.00
stress_all				4	10	40.00
	adc_ctrl_stress_all	118.700s	218887.391us	4	10	40.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.530s	532.491us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.250s	507.368us	10	10	100.00
tl_d_oob_addr_access				5	5	100.00
	adc_ctrl_tl_errors	3.120s	560.997us	5	5	100.00
tl_d_illegal_access				5	5	100.00
	adc_ctrl_tl_errors	3.120s	560.997us	5	5	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.410s	724.256us	1	1	100.00
	adc_ctrl_csr_rw	1.970s	535.112us	5	5	100.00
	adc_ctrl_csr_aliasing	4.900s	812.993us	1	1	100.00
	adc_ctrl_same_csr_outstanding	7.710s	4406.618us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.410s	724.256us	1	1	100.00
	adc_ctrl_csr_rw	1.970s	535.112us	5	5	100.00
	adc_ctrl_csr_aliasing	4.900s	812.993us	1	1	100.00
	adc_ctrl_same_csr_outstanding	7.710s	4406.618us	5	5	100.00

V2S

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				10	10	100.00
	adc_ctrl_sec_cm	15.180s	7822.438us	5	5	100.00
	adc_ctrl_tl_intg_err	24.810s	8631.248us	5	5	100.00
sec_cm_bus_integrity				5	5	100.00
	adc_ctrl_tl_intg_err	24.810s	8631.248us	5	5	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	adc_ctrl_stress_all_with_rand_reset	8.140s	23680.108us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				96 test runs
	adc_ctrl_filters_polled	49208378621912526597821609687867223048746694307308236611389836860498519016086	389	UVM_INFO @ 474437200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	75337314427572408681659700217703896623296714977806089310671367289649174989090	389	UVM_INFO @ 430887170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	8737426913115115148010823173039559344362404705855615461775846855531446956948	389	UVM_INFO @ 274573481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	65541153887599993337576155771422521577125490914444453692638671656031932412182	389	UVM_INFO @ 292853312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	67122780867714296311911551185543946074496504748112342216260822058682496252792	389	UVM_INFO @ 387367793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	65912560082171088759532952502545797853654669691541003567259778559487989400088	389	UVM_INFO @ 448753159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	99682894778954740527974780634799047697213304656486059621772655331093616626609	389	UVM_INFO @ 504921462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	49502841928202402054213083322283383795700415787977678701657956286254066795894	389	UVM_INFO @ 482614921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	63291227474461489102552258477278887889559776609988751647708359569450990031127	395	UVM_INFO @ 796994058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	42470717830596124037572821106741870904931613642082627922157992494911713736395	389	UVM_INFO @ 302739615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	33628426563687255673629129219959011415422434455286304838856944173510019719488	389	UVM_INFO @ 296132917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	90252242061861064883543169773667659331796327089883285819445542524644534793135	389	UVM_INFO @ 326241957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	49645996506037318185509386610960480361914842208675856646078111876150706834312	389	UVM_INFO @ 483745588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	104189086872496362098285271197122547168211189305613203615701035726991392030354	389	UVM_INFO @ 302904703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	43819670243893316808883747264770360730621539697947767108676152096328190186269	389	UVM_INFO @ 301072871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	36640401735897134607037681398644021534248609278123106823451387018552882501802	389	UVM_INFO @ 397499574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	33198271214332941811028932169633561884399287948927101605696285518465911394157	389	UVM_INFO @ 429840569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	65677961922997335596159868599976742789066629032703001815984300924070543706921	408	UVM_INFO @ 1511218599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	3758965096611596504860586895023541899449590538379501782791388393867150916397	390	UVM_INFO @ 699782972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	30030939815254129151244416570625070599420908448299019235572487583194374174190	389	UVM_INFO @ 502141344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	77024330259913789151463463898026301724088608978338113710073142970989714871782	389	UVM_INFO @ 282367325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	109952255793077722657464628220962228800955271825663719969640087646059452599279	389	UVM_INFO @ 454591533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	110849642956375333220333633649732351565178334642754560717116295101576667202737	389	UVM_INFO @ 371949849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	113485796120968697321328217566005915900529383211452214861954020733646470610473	389	UVM_INFO @ 458036833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	106140028690722816084580331393030577436287979202013190274130297309226494612870	389	UVM_INFO @ 309831623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	71844575354353978047248040643523592658296070411967367211037988452703534402382	389	UVM_INFO @ 384102835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	34509205625834028943796836216416508281831850137175214465818530426001048709595	389	UVM_INFO @ 523277664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	20298526303159135593176176786539927574177808931233834610065021212579247236096	515	UVM_INFO @ 23680108079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	43430251243133981126793585343748554677150930808410225763053715094954503274464	417	UVM_INFO @ 93207727407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	12067953835451265439855480044664863119035716508881139740931715930835933362458	389	UVM_INFO @ 436163189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	65434195065841035942100063190079470838225622832843005177275563851153871266792	389	UVM_INFO @ 435372203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	98609595851695742305961198285805963953482780288553683674913570279937717310280	389	UVM_INFO @ 486460420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	59448113505625001029604330615448871800381342267995716312025183555941406774560	389	UVM_INFO @ 507096870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	107931326205201257733247938304219466273582347268157790940608373482497719189210	389	UVM_INFO @ 328738681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	44180248286914364816787752376906333891429569650804321408508607825383884312516	389	UVM_INFO @ 407629956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	81308698484111393311835143804446034905749260285452520746233030810919615666304	389	UVM_INFO @ 418375225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	26851475417688506824027407260639313191417606057723282164634781066375519326171	389	UVM_INFO @ 415338082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	71331586072117328705513881598938624187390514839996155988809207705342963998741	413	UVM_INFO @ 2008401795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	113791125239605490888679737299674795132862629496796442370202627948929299210636	430	UVM_INFO @ 95252649144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	88865725191956459079994528139489264894314639863813776422003196331042465181619	389	UVM_INFO @ 472421252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	24224207770156688557111256554580328923444769655189203864983610855826724752545	389	UVM_INFO @ 341581204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	110947141056286434885965381375121183201759494175757364451224694800968331800880	389	UVM_INFO @ 289299032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	51854383571116029207127427760405565330132589181582155265555577643624750670676	389	UVM_INFO @ 480308383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	43734896271004505610535815561776549108272147842512156261381906378434713869404	389	UVM_INFO @ 379689456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	102835756744963551440582641329938961026131975748723364971037726323228668602790	389	UVM_INFO @ 342027642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	80986702449231980997946531670242690773206159050502013725265916890994467209585	389	UVM_INFO @ 493779074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	75197423727310835882361747611778828714158515285673236467469013576516249102134	389	UVM_INFO @ 305815187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	43289703721678585949292517486767250420067063063172930420805427888864151778060	395	UVM_INFO @ 952820010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	67090751894541271803238844435476159979248973059401564546839023166741196151203	389	UVM_INFO @ 356729855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	14977996306712327996564459720798468098757841252790088973889937420111396702170	389	UVM_INFO @ 458002433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	113424921826606408614979355101541847538918508937052451708869023927835855540888	389	UVM_INFO @ 506934473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	74747709682343835476763617692719099495333451849364160222667879860499814124611	389	UVM_INFO @ 508184721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	22686968760546822944020237602504238349002934726746990094989127642897974975454	389	UVM_INFO @ 340926168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	66434973972156149704108178112741016410185557369851692926638253676812875770103	389	UVM_INFO @ 458568014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	77703972257545544002333557058272106245353554131717662033576357481613275293063	389	UVM_INFO @ 462156396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	92088937182139470705214401952762392303265562487600853902435684514683868915585	389	UVM_INFO @ 357595542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	109482657271321981859339914654787796188190496918064733152043613506273872927562	422	UVM_INFO @ 2433514490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	42347194093794219630869177003965739125144833346473385408592159306528413026459	389	UVM_INFO @ 463408042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	61925390214554990374820380491906376861020617399308077352268163823581942419101	389	UVM_INFO @ 397368656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	74316337422936856796328424088999799874729470173115790670457522880791594124528	389	UVM_INFO @ 329387330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	71232847666384625333215176412082472368590693401581487021972954849337962644200	389	UVM_INFO @ 369780275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	115276591304534309782829078565927339080636613473169490424520480080639357825437	389	UVM_INFO @ 431821314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	31449992285561118502299223988776729692211365168988217574037168788170651235754	389	UVM_INFO @ 342971944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	105684668377015150035652001004517494934138595295879967381712023945421648345714	389	UVM_INFO @ 450172908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	38127757749627269824616586196881408437697529870866840734825718726788339303018	389	UVM_INFO @ 365113430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	2443243378346391986413027050244202563074322265507211004541117845676487202856	442	UVM_INFO @ 10263325384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	78780819438241253505505610007440467868407259572109339183325227990177027276063	390	UVM_INFO @ 800630624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	90503454253356927061895192045320555911249102609650484113022522577863784289811	389	UVM_INFO @ 370563703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	38806363871149046230275822589697452332252075895668227474809282647367466379662	389	UVM_INFO @ 385709702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	107517508893388869398946977081941638088258763181249925457691731313008170536699	389	UVM_INFO @ 446757439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	37366630545595013718498221340141540315273853083740202377188776346427669574290	389	UVM_INFO @ 286106191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	46030205806706507472510563985291240982177583077055171020853603877860204730045	389	UVM_INFO @ 397983488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	41131866715090061606347796915185097998218050314223740541464370249094884710257	389	UVM_INFO @ 489780739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	23096267257734437246244603123661417919887968333666644676356950901397282552430	389	UVM_INFO @ 286578250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	93772242150797479452263865345980443806287953246219990258279356823299460088119	389	UVM_INFO @ 313774301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	31560502261624757339366529274711106677389020926849963441731871599058697074418	447	UVM_INFO @ 17572619828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	74122538562768828651199443272915862673201503009601202289531834870767477446922	390	UVM_INFO @ 801382657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	58060759038401659852164162190270438302518535586681038580418900874969960655177	389	UVM_INFO @ 347662139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	26799684105625907606146672057324106334923356562747584867351831853054600687769	389	UVM_INFO @ 393215656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	112361192986779169840035496065975259528708495589626281609583700137422546702782	389	UVM_INFO @ 513791284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	2027109675688399632295915719158405973263867917035301634466134393812609589106	389	UVM_INFO @ 415054767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	63530821226097999443441791060182778308382795958700745276307161374813462334433	389	UVM_INFO @ 323736502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	79197007682270951849812634009236316593558617193987618371007020015971183707090	389	UVM_INFO @ 326776478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	25016897319722609603247446021615554835437025892569092793151985647843863509592	389	UVM_INFO @ 279121815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	54774428876208809201013030638345640827274346914222296959347604533070587815889	389	UVM_INFO @ 281664974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	1010725236819807850443796541459558554405403146931979818045151291353848587451	423	UVM_INFO @ 900123840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	42093486657254412583801891621832772172195516554750303552520826820015772891511	389	UVM_INFO @ 307906644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	32746394164900504060071038847223619962241272856226534634510111609438630808536	389	UVM_INFO @ 431841802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	45679251104174052306441218258194107212106727790378023447645844853701778705427	389	UVM_INFO @ 488402848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	31332605096919732115042764469085501916887056847192334710204224601659268718293	389	UVM_INFO @ 449376227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	33900431883314365080155819525938950599698078795626493731326817943881619661007	389	UVM_INFO @ 383059173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	64502811929112138760861761189720174968206816523265898719168367815333015225269	389	UVM_INFO @ 491636147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	23874178130225397818361560484992874443683318838081262440443172060004890797797	389	UVM_INFO @ 489265613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	56692611824588412769764093576199322837270303363395809131558272663476301639016	389	UVM_INFO @ 380271134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	52296396514775258025089994808519635685834365293610606681773543305532402593510	456	UVM_INFO @ 3362694388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	84680107558851491615133768301162791103050924167533321880412237272047851177857	412	UVM_INFO @ 5245707497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---