Simulation Results

Simulation Results: aes/masked

08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: xcelium [unknown]

Coverage statistics

Total
96.12 %

code
97.50 %

assert
98.57 %

func
92.28 %

block
97.37 %

line
98.96 %

branch
92.99 %

toggle
98.05 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		92.14%
V2S		94.80%
V3		10.00%

24/24 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	aes_wake_up	2.000s	80.891us	1	1	100.00
smoke				10	10	100.00
	aes_smoke	14.000s	607.762us	10	10	100.00
csr_hw_reset				1	1	100.00
	aes_csr_hw_reset	2.000s	106.052us	1	1	100.00
csr_rw				5	5	100.00
	aes_csr_rw	3.000s	84.945us	5	5	100.00
csr_bit_bash				1	1	100.00
	aes_csr_bit_bash	5.000s	289.953us	1	1	100.00
csr_aliasing				1	1	100.00
	aes_csr_aliasing	3.000s	70.594us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	aes_csr_mem_rw_with_rand_reset	3.000s	69.588us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	aes_csr_rw	3.000s	84.945us	5	5	100.00
	aes_csr_aliasing	3.000s	70.594us	1	1	100.00

211/229 passed

92.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
algorithm				30	30	100.00
	aes_smoke	14.000s	607.762us	10	10	100.00
	aes_config_error	34.000s	1070.990us	10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
key_length				30	30	100.00
	aes_smoke	14.000s	607.762us	10	10	100.00
	aes_config_error	34.000s	1070.990us	10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
back2back				20	20	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
	aes_b2b	34.000s	354.732us	10	10	100.00
backpressure				10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
multi_message				31	40	77.50
	aes_smoke	14.000s	607.762us	10	10	100.00
	aes_config_error	34.000s	1070.990us	10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
	aes_alert_reset	82.000s	10005.626us	1	10	10.00
failure_test				21	30	70.00
	aes_man_cfg_err	3.000s	61.026us	10	10	100.00
	aes_config_error	34.000s	1070.990us	10	10	100.00
	aes_alert_reset	82.000s	10005.626us	1	10	10.00
trigger_clear_test				10	10	100.00
	aes_clear	28.000s	146.432us	10	10	100.00
nist_test_vectors				1	1	100.00
	aes_nist_vectors	11.000s	329.390us	1	1	100.00
nist_test_vectors_gcm				1	1	100.00
	aes_nist_vectors_gcm	10.000s	1830.377us	1	1	100.00
reset_recovery				1	10	10.00
	aes_alert_reset	82.000s	10005.626us	1	10	10.00
stress				10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
sideload				20	20	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
	aes_sideload	6.000s	452.639us	10	10	100.00
deinitialization				10	10	100.00
	aes_deinit	5.000s	180.803us	10	10	100.00
stress_all				1	10	10.00
	aes_stress_all	200.000s	13207.198us	1	10	10.00
gcm_save_and_restore				100	100	100.00
	aes_gcm_save_restore	25.000s	1364.227us	100	100	100.00
alert_test				10	10	100.00
	aes_alert_test	27.000s	64.815us	10	10	100.00
tl_d_oob_addr_access				5	5	100.00
	aes_tl_errors	3.000s	89.989us	5	5	100.00
tl_d_illegal_access				5	5	100.00
	aes_tl_errors	3.000s	89.989us	5	5	100.00
tl_d_outstanding_access				12	12	100.00
	aes_csr_hw_reset	2.000s	106.052us	1	1	100.00
	aes_csr_rw	3.000s	84.945us	5	5	100.00
	aes_csr_aliasing	3.000s	70.594us	1	1	100.00
	aes_same_csr_outstanding	3.000s	137.711us	5	5	100.00
tl_d_partial_access				12	12	100.00
	aes_csr_hw_reset	2.000s	106.052us	1	1	100.00
	aes_csr_rw	3.000s	84.945us	5	5	100.00
	aes_csr_aliasing	3.000s	70.594us	1	1	100.00
	aes_same_csr_outstanding	3.000s	137.711us	5	5	100.00

V2S

967/1020 passed

94.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reseeding				10	10	100.00
	aes_reseed	30.000s	917.781us	10	10	100.00
fault_inject				626	660	94.85
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_cipher_fi	61.000s	10003.143us	341	350	97.43
shadow_reg_update_error				5	5	100.00
	aes_shadow_reg_errors	3.000s	241.378us	5	5	100.00
shadow_reg_read_clear_staged_value				5	5	100.00
	aes_shadow_reg_errors	3.000s	241.378us	5	5	100.00
shadow_reg_storage_error				5	5	100.00
	aes_shadow_reg_errors	3.000s	241.378us	5	5	100.00
shadowed_reset_glitch				5	5	100.00
	aes_shadow_reg_errors	3.000s	241.378us	5	5	100.00
shadow_reg_update_error_with_csr_rw				5	5	100.00
	aes_shadow_reg_errors_with_csr_rw	4.000s	433.350us	5	5	100.00
tl_intg_err				10	10	100.00
	aes_sec_cm	9.000s	1086.937us	5	5	100.00
	aes_tl_intg_err	3.000s	415.229us	5	5	100.00
sec_cm_bus_integrity				5	5	100.00
	aes_tl_intg_err	3.000s	415.229us	5	5	100.00
sec_cm_lc_escalate_en_intersig_mubi				1	10	10.00
	aes_alert_reset	82.000s	10005.626us	1	10	10.00
sec_cm_main_config_shadow				5	5	100.00
	aes_shadow_reg_errors	3.000s	241.378us	5	5	100.00
sec_cm_gcm_config_shadow				5	5	100.00
	aes_shadow_reg_errors	3.000s	241.378us	5	5	100.00
sec_cm_main_config_sparse				81	100	81.00
	aes_smoke	14.000s	607.762us	10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
	aes_alert_reset	82.000s	10005.626us	1	10	10.00
	aes_core_fi	74.000s	10010.963us	60	70	85.71
sec_cm_gcm_config_sparse				180	190	94.74
	aes_gcm_save_restore	25.000s	1364.227us	100	100	100.00
	aes_config_error	34.000s	1070.990us	10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
	aes_core_fi	74.000s	10010.963us	60	70	85.71
sec_cm_aux_config_shadow				5	5	100.00
	aes_shadow_reg_errors	3.000s	241.378us	5	5	100.00
sec_cm_aux_config_regwen				20	20	100.00
	aes_readability	5.000s	114.234us	10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
sec_cm_key_sideload				20	20	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
	aes_sideload	6.000s	452.639us	10	10	100.00
sec_cm_key_sw_unreadable				10	10	100.00
	aes_readability	5.000s	114.234us	10	10	100.00
sec_cm_data_reg_sw_unreadable				10	10	100.00
	aes_readability	5.000s	114.234us	10	10	100.00
sec_cm_key_sec_wipe				10	10	100.00
	aes_readability	5.000s	114.234us	10	10	100.00
sec_cm_iv_config_sec_wipe				10	10	100.00
	aes_readability	5.000s	114.234us	10	10	100.00
sec_cm_data_reg_sec_wipe				10	10	100.00
	aes_readability	5.000s	114.234us	10	10	100.00
sec_cm_data_reg_key_sca				10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
sec_cm_key_masking				10	10	100.00
	aes_stress	10.000s	387.159us	10	10	100.00
sec_cm_main_fsm_sparse				0	10	0.00
	aes_fi	91.000s	10011.288us	0	10	0.00
sec_cm_main_fsm_redun				636	670	94.93
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_cipher_fi	61.000s	10003.143us	341	350	97.43
	aes_ctr_fi	23.000s	53.544us	10	10	100.00
sec_cm_cipher_fsm_sparse				0	10	0.00
	aes_fi	91.000s	10011.288us	0	10	0.00
sec_cm_cipher_fsm_redun				626	660	94.85
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_cipher_fi	61.000s	10003.143us	341	350	97.43
sec_cm_cipher_ctr_redun				341	350	97.43
	aes_cipher_fi	61.000s	10003.143us	341	350	97.43
sec_cm_ctr_fsm_sparse				0	10	0.00
	aes_fi	91.000s	10011.288us	0	10	0.00
sec_cm_ctr_fsm_redun				295	320	92.19
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_ctr_fi	23.000s	53.544us	10	10	100.00
sec_cm_ghash_fsm_sparse				0	10	0.00
	aes_fi	91.000s	10011.288us	0	10	0.00
sec_cm_ctrl_sparse				636	670	94.93
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_cipher_fi	61.000s	10003.143us	341	350	97.43
	aes_ctr_fi	23.000s	53.544us	10	10	100.00
sec_cm_main_fsm_global_esc				1	10	10.00
	aes_alert_reset	82.000s	10005.626us	1	10	10.00
sec_cm_main_fsm_local_esc				636	670	94.93
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_cipher_fi	61.000s	10003.143us	341	350	97.43
	aes_ctr_fi	23.000s	53.544us	10	10	100.00
sec_cm_cipher_fsm_local_esc				636	670	94.93
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_cipher_fi	61.000s	10003.143us	341	350	97.43
	aes_ctr_fi	23.000s	53.544us	10	10	100.00
sec_cm_ctr_fsm_local_esc				295	320	92.19
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_ctr_fi	23.000s	53.544us	10	10	100.00
sec_cm_ghash_fsm_local_esc				90	100	90.00
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_ghash_fi	5.000s	140.248us	90	90	100.00
sec_cm_data_reg_local_esc				626	660	94.85
	aes_fi	91.000s	10011.288us	0	10	0.00
	aes_control_fi	61.000s	0.000us	285	300	95.00
	aes_cipher_fi	61.000s	10003.143us	341	350	97.43

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	aes_stress_all_with_rand_reset	112.000s	4179.578us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!				18 test runs
	aes_alert_reset	99029601087211919245141945150125978578521756134137637026711844301187681826684	3881	UVM_INFO @ 10211563050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	72772476347506848645046036869347924441393510150710345428199975612171793034097	83537	UVM_INFO @ 10251232971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	36245027769839670531053307967889925232631747782125426434920181314347509786270	1450	UVM_INFO @ 10031690273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	52015583342026098237760844859132028636656747024288425811334978517567954998536	960	UVM_INFO @ 10021293137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	51404343394925203147981450972701274046541749150267899092483636021816427754856	20430	UVM_INFO @ 11222461646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	6695697415033651535116295340570581659886932325280396993992530408205437224381	4344	UVM_INFO @ 10024323458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	55692227710348304126491037102509304700772303042198831104882704453182023256389	9517	UVM_INFO @ 10498671524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	79763827523375140958997117023661205184521133172028503612227190359903159720114	1393	UVM_INFO @ 10196960504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	13450900032861174454118231449673603254295706524312774609681508293666496535477	26523	UVM_INFO @ 10299677875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	35465065117295972128473976709819590233722428488115118413797834223365598493790	371	UVM_INFO @ 10007778635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	86287090792269651136760313788556330562445432177362939354356754165293352848837	45857	UVM_INFO @ 10636669147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	64991432015417913347026100208061917051219224164041220155407243604544236892991	1233	UVM_INFO @ 10005626201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	94519310143973641767532734336912344832976943133009903937803849332592979679200	374636	UVM_INFO @ 13207198159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	53300720548422486565748134473813045500945452817399981020277806373084044680530	743	UVM_INFO @ 10012289794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	105382042436511179592012413458147126874032262522852741861454978624383236580408	4640	UVM_INFO @ 10017674237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	68875812821926372904921961339479806180201108800375395689571972895038885132411	10170	UVM_INFO @ 10123439479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	52426676602929605493522758379391481591154653688675012842352802272534255014807	1202	UVM_INFO @ 10020582318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	70546523777456546922646846040437252435248676825440188223616104532882323380176	78904	UVM_INFO @ 10260601763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				11 test runs
	aes_control_fi	33959248433381278212917686834080785643083145690655386199920639249064108009307	None
	aes_control_fi	99881039663548618248085201481988271646350062971911411703359495555239011654383	None
	aes_control_fi	114092825283834542403968444163348617494668483660454374179775159075084369042804	None
	aes_cipher_fi	51874445824846826111243274845133537847846025195685054233371415419134442199612	None
	aes_control_fi	105234717394726468375560064219728166490265613849755756112787179164674047420352	None
	aes_control_fi	34473615768166415487843641041208827746227260831090630236020174153075909226183	None
	aes_cipher_fi	39979509386715703326552525349951419622458563508953607282680262100591058590378	None
	aes_control_fi	89220181241557620651271671802602197108241969443841701790929840070944762599326	None
	aes_control_fi	2641025970953753319632725900109435287915682757524166177743636797934636437027	None
	aes_cipher_fi	83253064135695678611191918505524022795045363282300561952813210036068868545495	None
	aes_control_fi	10701610506751590232295617430935741137375161548188023759952866908209146219892	None
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!				10 test runs
	aes_fi	99126370135825545495008992338403285003208108583641792771809630808305281776837	584	UVM_INFO @ 10037902431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	102392053211260823794331285674229309302245701729656593168883210284106362362532	2944	UVM_INFO @ 10011287505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	34391554010553809489401491381912948264715854095453794555116443872640938596441	4186	UVM_INFO @ 10025057163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	20890683936859525883514281994985241505149478945789073007247144931478199930258	485	UVM_INFO @ 10022078069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	59420339078619288301324646924815237487308548966202764227383736582575954024028	772	UVM_INFO @ 10026654866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	83172673985661878071981101010776238866884652954603787454204648389463508087358	671	UVM_INFO @ 10030922562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	115160675949874490455669135344503004200841798459378877246684658488245679991554	2256	UVM_INFO @ 10011745637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	96496601155026701011075314611325554031754255598003141893761559618023528745418	662	UVM_INFO @ 10011710875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	15458309507209623014351925050450200799231161987843581975811545556896526948141	648	UVM_INFO @ 10004637130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_fi	40140077868468759077077052924446015392783058848680473844650568605169536927673	3901	UVM_INFO @ 10025156971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_core_fi_vseq] wait timeout occurred!				8 test runs
	aes_core_fi	114418944793134260416491946487264387444693762698919748688345290433606138297701	140	UVM_INFO @ 10011915224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	46467576687310868298088142903186048536490979586061143175284647561003485012170	140	UVM_INFO @ 10011431332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	39534439289153626751319110729662454044661386438638839645172420287420203133630	140	UVM_INFO @ 10045338831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	91576077916791459047298571899889922123982285518159353548475422834730354568372	139	UVM_INFO @ 10141885685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	845956476159093475461986721917196181037246071607407785015062473907364413164	139	UVM_INFO @ 10072321868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	115789293499228626210429227243459593608320126139211532187192933393393033001536	144	UVM_INFO @ 10024982971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	23914189954005160889005764879250487110608532269416231324297159637656102078827	141	UVM_INFO @ 10010962574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	89734004224646671956695936266816646085803481270469208096395076537930576347662	140	UVM_INFO @ 10011464837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!				7 test runs
	aes_control_fi	88971236755180566977830038028824407060705077706594002563460241410281493322817	144	UVM_INFO @ 10010020362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	34491356192957100310632683661189867661736735699412524728227745860381022182089	148	UVM_INFO @ 10049514826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	105858793726735593770798015621330397716771734206830579710477237488329283738972	146	UVM_INFO @ 10008161814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	36205895142116108802790618648975675393846888193369370926878575135685545018702	154	UVM_INFO @ 10008004783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	114457717515068226099530143341672270655140487429825909515412821475177742024617	150	UVM_INFO @ 10033859870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	26124989947469130635996975180342335731455844232825496303343186138934760208357	158	UVM_INFO @ 10040874949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	91195644046976215788699782498156726249489679576551018054632846397129566189831	149	UVM_INFO @ 10012192462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!				6 test runs
	aes_cipher_fi	27303898314576008276687871500737361547499546701863260956732567872148665216889	151	UVM_INFO @ 10029313081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	77589084200740125942790734931262987449919027397543390961326136270644073620899	152	UVM_INFO @ 10043412590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	16741353476364147024706656051931343371045363297922426814378835714152236225255	153	UVM_INFO @ 10028847548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	6588263781337326343185506456327147492278280170608623769852606170702910965310	143	UVM_INFO @ 10016553766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	47597582999580603895974189165915692405603224384247592796854898417762863571503	143	UVM_INFO @ 10116861151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	108817234006377612249074422892988974384972577390324753250067106842904665315287	147	UVM_INFO @ 10016907552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				3 test runs
	aes_stress_all_with_rand_reset	67638169000819621567656060346887097696504242355837983741457157855180830006649	495	UVM_INFO @ 5742292998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	23217797930624663351437480718121961052825092799800257539819896299821897385320	181	UVM_INFO @ 885608066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	72445593814864920097170188648513947075162510492479279890978362560784805731456	2412	UVM_INFO @ 5457840372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues				2 test runs
	aes_stress_all_with_rand_reset	80039584760086138613118963287922333794646941877882325074139437168058476990923	1399	UVM_INFO @ 1587677821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	92670196503444769664193631369220598281322754080902687381123641414060539695965	3632	UVM_INFO @ 4179577521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!				2 test runs
	aes_core_fi	79837058151176016462245767896884865579322445493734018526677790524942625584911	149	UVM_INFO @ 10022778072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	3316952961539835221806905532791606441824004649760988815342428377855292012816	145	UVM_INFO @ 10006942028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_reseed_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG				1 test run
	aes_stress_all_with_rand_reset	67740205144018230163407645994584297988075583515626493005344140778586582568190	1769	UVM_INFO @ 2403907194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)				1 test run
	aes_stress_all_with_rand_reset	69733585869466572413530316102922019043591960095065733807560133606040385201277	214	UVM_INFO @ 760924540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (alert_receiver_driver.sv:219) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q				1 test run
	aes_stress_all_with_rand_reset	8873006396251391277055438277648427552560729988723104987160234513279628819786	1173	UVM_INFO @ 969747876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)				1 test run
	aes_stress_all_with_rand_reset	66639764551000315979405840624475184994556314224463651936894139092721016369436	434	UVM_INFO @ 697786108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---