Simulation Results: alert_handler

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.79 %
  • code
  • 97.58 %
  • assert
  • 98.88 %
  • func
  • 93.92 %
  • line
  • 99.91 %
  • branch
  • 99.89 %
  • cond
  • 96.32 %
  • toggle
  • 96.63 %
  • FSM
  • 95.16 %
Validation stages
V1
100.00%
V2
94.35%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
alert_handler_smoke 51.480s 951.286us 10 10 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.980s 24.112us 1 1 100.00
csr_rw 5 5 100.00
alert_handler_csr_rw 12.150s 470.247us 5 5 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 405.640s 7424.439us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 185.700s 17405.443us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.960s 72.908us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
alert_handler_csr_rw 12.150s 470.247us 5 5 100.00
alert_handler_csr_aliasing 185.700s 17405.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 10 10 100.00
alert_handler_esc_alert_accum 293.350s 17700.553us 10 10 100.00
esc_timeout 10 10 100.00
alert_handler_esc_intr_timeout 58.200s 3720.600us 10 10 100.00
entropy 10 10 100.00
alert_handler_entropy 2232.760s 98741.440us 10 10 100.00
sig_int_fail 10 10 100.00
alert_handler_sig_int_fail 56.750s 3130.017us 10 10 100.00
clk_skew 10 10 100.00
alert_handler_smoke 51.480s 951.286us 10 10 100.00
random_alerts 10 10 100.00
alert_handler_random_alerts 49.170s 954.003us 10 10 100.00
random_classes 10 10 100.00
alert_handler_random_classes 56.120s 908.872us 10 10 100.00
ping_timeout 0 10 0.00
alert_handler_ping_timeout 337.780s 10333.713us 0 10 0.00
lpg 20 20 100.00
alert_handler_lpg 2431.840s 322033.697us 10 10 100.00
alert_handler_lpg_stub_clk 2353.520s 47309.585us 10 10 100.00
stress_all 10 10 100.00
alert_handler_stress_all 1847.050s 82717.775us 10 10 100.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 67.410s 2752.400us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 5.230s 58.553us 20 20 100.00
intr_test 10 10 100.00
alert_handler_intr_test 2.040s 12.656us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
alert_handler_tl_errors 24.100s 289.672us 5 5 100.00
tl_d_illegal_access 5 5 100.00
alert_handler_tl_errors 24.100s 289.672us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
alert_handler_csr_hw_reset 3.980s 24.112us 1 1 100.00
alert_handler_csr_rw 12.150s 470.247us 5 5 100.00
alert_handler_csr_aliasing 185.700s 17405.443us 1 1 100.00
alert_handler_same_csr_outstanding 27.540s 278.388us 5 5 100.00
tl_d_partial_access 12 12 100.00
alert_handler_csr_hw_reset 3.980s 24.112us 1 1 100.00
alert_handler_csr_rw 12.150s 470.247us 5 5 100.00
alert_handler_csr_aliasing 185.700s 17405.443us 1 1 100.00
alert_handler_same_csr_outstanding 27.540s 278.388us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 5 5 100.00
alert_handler_shadow_reg_errors 298.720s 4764.121us 5 5 100.00
shadow_reg_read_clear_staged_value 5 5 100.00
alert_handler_shadow_reg_errors 298.720s 4764.121us 5 5 100.00
shadow_reg_storage_error 5 5 100.00
alert_handler_shadow_reg_errors 298.720s 4764.121us 5 5 100.00
shadowed_reset_glitch 5 5 100.00
alert_handler_shadow_reg_errors 298.720s 4764.121us 5 5 100.00
shadow_reg_update_error_with_csr_rw 5 5 100.00
alert_handler_shadow_reg_errors_with_csr_rw 691.950s 9485.799us 5 5 100.00
tl_intg_err 10 10 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
alert_handler_tl_intg_err 61.350s 1731.021us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
alert_handler_tl_intg_err 61.350s 1731.021us 5 5 100.00
sec_cm_config_shadow 5 5 100.00
alert_handler_shadow_reg_errors 298.720s 4764.121us 5 5 100.00
sec_cm_ping_timer_config_regwen 10 10 100.00
alert_handler_smoke 51.480s 951.286us 10 10 100.00
sec_cm_alert_config_regwen 10 10 100.00
alert_handler_smoke 51.480s 951.286us 10 10 100.00
sec_cm_alert_loc_config_regwen 10 10 100.00
alert_handler_smoke 51.480s 951.286us 10 10 100.00
sec_cm_class_config_regwen 10 10 100.00
alert_handler_smoke 51.480s 951.286us 10 10 100.00
sec_cm_alert_intersig_diff 10 10 100.00
alert_handler_sig_int_fail 56.750s 3130.017us 10 10 100.00
sec_cm_lpg_intersig_mubi 10 10 100.00
alert_handler_lpg 2431.840s 322033.697us 10 10 100.00
sec_cm_esc_intersig_diff 10 10 100.00
alert_handler_sig_int_fail 56.750s 3130.017us 10 10 100.00
sec_cm_alert_rx_intersig_bkgn_chk 10 10 100.00
alert_handler_entropy 2232.760s 98741.440us 10 10 100.00
sec_cm_esc_tx_intersig_bkgn_chk 10 10 100.00
alert_handler_entropy 2232.760s 98741.440us 10 10 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 39.580s 1236.716us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
alert_handler_stress_all_with_rand_reset 259.740s 6470.577us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 10 test runs
alert_handler_ping_timeout 19253406250427331570913513435930177391388505060633716725129748471179311650188 94
UVM_INFO @ 3644099037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 84800531764393067804374914608491584610675484178211168732816069572249738729177 87
UVM_INFO @ 2157804856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 94286098078651431309540193393241003974767334294544730380484604443240705093658 96
UVM_INFO @ 1679718570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 30345763743777229608691522955912094493874972081372247230781492023531729217128 143
UVM_INFO @ 10333713383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 71120875567757916598804122676228776425030518601431145256499852712480531351405 102
UVM_INFO @ 3325819637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 73671229204589162099115325225650546685688398428049845484027196870678345077190 87
UVM_INFO @ 841423421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 14613568998702202961279462061337094783046820306266451716316462668903016519577 111
UVM_INFO @ 2821660217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 41838029487924677991636394483693105019852912935750511065136073085912677928982 87
UVM_INFO @ 3815443583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 77039808233190096237260054808358350198342513481163139996065096955695554968189 90
UVM_INFO @ 5713193958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 69489674250404997714878165187028262667299488434678316891877799955802541121130 105
UVM_INFO @ 2993582128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
alert_handler_stress_all_with_rand_reset 77128109148922565033517138826146873289878054106112592414651033457410823504116 146
UVM_INFO @ 9875301024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 43556830709587705136105627404733455622996303485507855637091535663122574781224 106
UVM_INFO @ 497894738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 22815247237333974615300656651812287085555894863075681529497749721642482792581 106
UVM_INFO @ 2788525992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 76735527807352715075785570591145925170603990515291923139223579268780490419336 82
UVM_INFO @ 686683022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 73910204515702820870990993352114330132200846536245239687102801192895947978000 83
UVM_INFO @ 110087207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 85896740555921718090873007308562655619847566060474484237768843472779966551246 82
UVM_INFO @ 1505525357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---