| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 2.550s | 700.880us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.990s | 1125.820us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| aon_timer_csr_rw | 1.710s | 347.885us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 4.280s | 7197.952us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 2.360s | 510.151us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 1.990s | 457.448us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| aon_timer_csr_rw | 1.710s | 347.885us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 2.360s | 510.151us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 1.700s | 392.287us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 1.870s | 388.815us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 79.060s | 42951.636us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 1.390s | 762.809us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 131.910s | 91701.937us | 15 | 15 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| aon_timer_alert_test | 1.890s | 517.857us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| aon_timer_intr_test | 2.000s | 472.023us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 5 | 5 | 100.00 | |||
| aon_timer_tl_errors | 3.420s | 602.916us | 5 | 5 | 100.00 | |
| tl_d_illegal_access | 5 | 5 | 100.00 | |||
| aon_timer_tl_errors | 3.420s | 602.916us | 5 | 5 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.990s | 1125.820us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 1.710s | 347.885us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 2.360s | 510.151us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 4.480s | 1135.456us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.990s | 1125.820us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 1.710s | 347.885us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 2.360s | 510.151us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 4.480s | 1135.456us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 10 | 10 | 100.00 | |||
| aon_timer_sec_cm | 17.960s | 7914.146us | 5 | 5 | 100.00 | |
| aon_timer_tl_intg_err | 22.030s | 8030.171us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 5 | 5 | 100.00 | |||
| aon_timer_tl_intg_err | 22.030s | 8030.171us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 2.350s | 537.494us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 2.000s | 710.276us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 10.870s | 3633.962us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 2.400s | 621.745us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 20.800s | 4090.716us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 47.860s | 42471.713us | 15 | 15 | 100.00 | |