| V1 |
|
96.09% |
| V2 |
|
86.21% |
| V2S |
|
100.00% |
| V3 |
|
83.02% |
| unmapped |
|
64.29% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_example_tests | 12 | 12 | 100.00 | |||
| chip_sw_example_flash | 202.380s | 2520.863us | 3 | 3 | 100.00 | |
| chip_sw_example_rom | 136.890s | 2650.616us | 3 | 3 | 100.00 | |
| chip_sw_example_manufacturer | 224.740s | 2798.222us | 3 | 3 | 100.00 | |
| chip_sw_example_concurrency | 198.050s | 3161.575us | 3 | 3 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| chip_csr_hw_reset | 396.340s | 7742.259us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| chip_csr_rw | 635.680s | 6747.283us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| chip_csr_bit_bash | 5199.050s | 57023.510us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| chip_csr_aliasing | 4584.660s | 29125.997us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 5 | 0.00 | |||
| chip_csr_mem_rw_with_rand_reset | 459.610s | 6045.245us | 0 | 5 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| chip_csr_aliasing | 4584.660s | 29125.997us | 1 | 1 | 100.00 | |
| chip_csr_rw | 635.680s | 6747.283us | 5 | 5 | 100.00 | |
| xbar_smoke | 50 | 50 | 100.00 | |||
| xbar_smoke | 12.220s | 259.802us | 50 | 50 | 100.00 | |
| chip_sw_gpio_out | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 393.640s | 4770.750us | 3 | 3 | 100.00 | |
| chip_sw_gpio_in | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 393.640s | 4770.750us | 3 | 3 | 100.00 | |
| chip_sw_gpio_irq | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 393.640s | 4770.750us | 3 | 3 | 100.00 | |
| chip_sw_uart_tx_rx | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 531.240s | 4727.122us | 5 | 5 | 100.00 | |
| chip_sw_uart_rx_overflow | 20 | 20 | 100.00 | |||
| chip_sw_uart_tx_rx | 531.240s | 4727.122us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx1 | 510.850s | 4354.527us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx2 | 531.790s | 4576.839us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx3 | 536.420s | 4312.234us | 5 | 5 | 100.00 | |
| chip_sw_uart_baud_rate | 20 | 20 | 100.00 | |||
| chip_sw_uart_rand_baudrate | 2906.440s | 13473.983us | 20 | 20 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 10 | 10 | 100.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 2435.590s | 13490.523us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 870.410s | 8593.047us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_pin_mux | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 302.410s | 5369.724us | 10 | 10 | 100.00 | |
| chip_padctrl_attributes | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 302.410s | 5369.724us | 10 | 10 | 100.00 | |
| chip_sw_sleep_pin_mio_dio_val | 0 | 3 | 0.00 | |||
| chip_sw_sleep_pin_mio_dio_val | 273.730s | 2831.475us | 0 | 3 | 0.00 | |
| chip_sw_sleep_pin_wake | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_wake | 521.720s | 6730.593us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pin_retention | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_retention | 271.290s | 4850.416us | 3 | 3 | 100.00 | |
| chip_sw_tap_strap_sampling | 20 | 20 | 100.00 | |||
| chip_tap_straps_dev | 1603.450s | 15811.960us | 5 | 5 | 100.00 | |
| chip_tap_straps_testunlock0 | 469.470s | 6589.072us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 861.480s | 10747.611us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 516.850s | 7666.774us | 5 | 5 | 100.00 | |
| chip_sw_pattgen_ios | 3 | 3 | 100.00 | |||
| chip_sw_pattgen_ios | 252.980s | 3229.955us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pwm_pulses | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pwm_pulses | 1126.690s | 9112.278us | 3 | 3 | 100.00 | |
| chip_sw_data_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 582.090s | 6107.439us | 6 | 6 | 100.00 | |
| chip_sw_instruction_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 582.090s | 6107.439us | 6 | 6 | 100.00 | |
| chip_sw_ast_clk_outputs | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 779.650s | 8663.055us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_rst_inputs | 2150.990s | 13614.684us | 0 | 3 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 448.430s | 4697.617us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 806.860s | 5876.907us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4633.540s | 19030.581us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 273.510s | 3282.934us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 1029.920s | 8705.852us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 257.970s | 3252.687us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 990.780s | 6013.655us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 246.360s | 3236.216us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 454.120s | 4771.830us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 233.290s | 3145.382us | 3 | 3 | 100.00 | |
| chip_sw_ast_usb_clk_calib | 1 | 1 | 100.00 | |||
| chip_sw_usb_ast_clk_calib | 221.880s | 3349.161us | 1 | 1 | 100.00 | |
| chip_sw_sensor_ctrl_ast_alerts | 8 | 8 | 100.00 | |||
| chip_sw_sensor_ctrl_alert | 654.600s | 9175.201us | 5 | 5 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 392.770s | 4730.606us | 3 | 3 | 100.00 | |
| chip_sw_sensor_ctrl_ast_status | 3 | 3 | 100.00 | |||
| chip_sw_sensor_ctrl_status | 209.040s | 3379.333us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 392.770s | 4730.606us | 3 | 3 | 100.00 | |
| chip_sw_smoketest | 51 | 51 | 100.00 | |||
| chip_sw_flash_scrambling_smoketest | 193.680s | 3282.472us | 3 | 3 | 100.00 | |
| chip_sw_aes_smoketest | 281.770s | 3026.649us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_smoketest | 285.390s | 3031.293us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_smoketest | 260.510s | 3300.768us | 3 | 3 | 100.00 | |
| chip_sw_csrng_smoketest | 249.650s | 3144.912us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_smoketest | 1317.620s | 7522.662us | 3 | 3 | 100.00 | |
| chip_sw_gpio_smoketest | 314.440s | 3266.656us | 3 | 3 | 100.00 | |
| chip_sw_hmac_smoketest | 229.790s | 3175.627us | 3 | 3 | 100.00 | |
| chip_sw_kmac_smoketest | 262.750s | 3306.648us | 3 | 3 | 100.00 | |
| chip_sw_otbn_smoketest | 1385.500s | 8074.981us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 419.980s | 5516.061us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usbdev_smoketest | 440.530s | 5931.428us | 3 | 3 | 100.00 | |
| chip_sw_rv_plic_smoketest | 237.390s | 3346.564us | 3 | 3 | 100.00 | |
| chip_sw_rv_timer_smoketest | 229.990s | 3098.975us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_smoketest | 233.480s | 2852.329us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 203.990s | 2927.828us | 3 | 3 | 100.00 | |
| chip_sw_uart_smoketest | 245.050s | 2928.793us | 3 | 3 | 100.00 | |
| chip_sw_otp_smoketest | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_smoketest | 212.870s | 3086.508us | 3 | 3 | 100.00 | |
| chip_sw_rom_functests | 0 | 3 | 0.00 | |||
| rom_keymgr_functest | 534.790s | 4389.898us | 0 | 3 | 0.00 | |
| chip_sw_boot | 3 | 3 | 100.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 12699.930s | 63328.887us | 3 | 3 | 100.00 | |
| chip_sw_secure_boot | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3704.390s | 15454.634us | 3 | 3 | 100.00 | |
| chip_sw_rom_raw_unlock | 0 | 3 | 0.00 | |||
| rom_raw_unlock | 237.487s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_power_idle_load | 0 | 3 | 0.00 | |||
| chip_sw_power_idle_load | 242.030s | 3103.125us | 0 | 3 | 0.00 | |
| chip_sw_power_sleep_load | 0 | 3 | 0.00 | |||
| chip_sw_power_sleep_load | 235.040s | 3591.562us | 0 | 3 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 3 | 3 | 100.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 11086.520s | 54757.569us | 3 | 3 | 100.00 | |
| chip_sw_inject_scramble_seed | 3 | 3 | 100.00 | |||
| chip_sw_inject_scramble_seed | 11416.720s | 59560.760us | 3 | 3 | 100.00 | |
| tl_d_oob_addr_access | 3 | 30 | 10.00 | |||
| chip_tl_errors | 500.860s | 4529.645us | 3 | 30 | 10.00 | |
| tl_d_illegal_access | 3 | 30 | 10.00 | |||
| chip_tl_errors | 500.860s | 4529.645us | 3 | 30 | 10.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| chip_csr_aliasing | 4584.660s | 29125.997us | 1 | 1 | 100.00 | |
| chip_same_csr_outstanding | 4614.910s | 31039.905us | 5 | 5 | 100.00 | |
| chip_csr_hw_reset | 396.340s | 7742.259us | 1 | 1 | 100.00 | |
| chip_csr_rw | 635.680s | 6747.283us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| chip_csr_aliasing | 4584.660s | 29125.997us | 1 | 1 | 100.00 | |
| chip_same_csr_outstanding | 4614.910s | 31039.905us | 5 | 5 | 100.00 | |
| chip_csr_hw_reset | 396.340s | 7742.259us | 1 | 1 | 100.00 | |
| chip_csr_rw | 635.680s | 6747.283us | 5 | 5 | 100.00 | |
| xbar_base_random_sequence | 50 | 50 | 100.00 | |||
| xbar_random | 83.300s | 2119.606us | 50 | 50 | 100.00 | |
| xbar_random_delay | 300 | 300 | 100.00 | |||
| xbar_smoke_zero_delays | 8.380s | 55.664us | 50 | 50 | 100.00 | |
| xbar_smoke_large_delays | 104.550s | 10051.237us | 50 | 50 | 100.00 | |
| xbar_smoke_slow_rsp | 88.000s | 7057.060us | 50 | 50 | 100.00 | |
| xbar_random_zero_delays | 56.780s | 620.491us | 50 | 50 | 100.00 | |
| xbar_random_large_delays | 416.630s | 51024.634us | 50 | 50 | 100.00 | |
| xbar_random_slow_rsp | 439.910s | 34435.596us | 50 | 50 | 100.00 | |
| xbar_unmapped_address | 100 | 100 | 100.00 | |||
| xbar_unmapped_addr | 56.930s | 1326.789us | 50 | 50 | 100.00 | |
| xbar_error_and_unmapped_addr | 51.180s | 1334.097us | 50 | 50 | 100.00 | |
| xbar_error_cases | 100 | 100 | 100.00 | |||
| xbar_error_random | 84.100s | 2436.067us | 50 | 50 | 100.00 | |
| xbar_error_and_unmapped_addr | 51.180s | 1334.097us | 50 | 50 | 100.00 | |
| xbar_all_access_same_device | 100 | 100 | 100.00 | |||
| xbar_access_same_device | 126.680s | 3149.330us | 50 | 50 | 100.00 | |
| xbar_access_same_device_slow_rsp | 1030.170s | 80671.374us | 50 | 50 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 50 | 50 | 100.00 | |||
| xbar_same_source | 79.670s | 2543.874us | 50 | 50 | 100.00 | |
| xbar_stress_all | 100 | 100 | 100.00 | |||
| xbar_stress_all | 669.460s | 18874.414us | 50 | 50 | 100.00 | |
| xbar_stress_all_with_error | 611.610s | 22195.775us | 50 | 50 | 100.00 | |
| xbar_stress_with_reset | 100 | 100 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 740.470s | 17897.288us | 50 | 50 | 100.00 | |
| xbar_stress_all_with_reset_error | 652.260s | 18594.931us | 50 | 50 | 100.00 | |
| rom_e2e_smoke | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3704.390s | 15454.634us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_output | 2 | 3 | 66.67 | |||
| rom_e2e_shutdown_output | 3646.230s | 27084.249us | 2 | 3 | 66.67 | |
| rom_e2e_shutdown_exception_c | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_exception_c | 3776.740s | 15161.743us | 3 | 3 | 100.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 278.412s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 60.160s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 85.381s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 48.792s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 32.120s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 124.308s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 85.145s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 63.057s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 71.218s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 119.272s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 118.211s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 168.993s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 98.040s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 137.107s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 88.882s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 119.105s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 41.743s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 34.405s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 28.070s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 57.388s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 120.651s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 94.749s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 35.755s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 93.976s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 14.517s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 126.741s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 53.293s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 53.494s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 19.916s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 58.163s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 15 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 105.966s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_dev | 148.858s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod | 27.177s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod_end | 186.194s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_rma | 123.645s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init | 6 | 9 | 66.67 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 7407.740s | 29474.320us | 1 | 3 | 33.33 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 7441.320s | 30311.583us | 2 | 3 | 66.67 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 7659.840s | 29916.496us | 3 | 3 | 100.00 | |
| rom_e2e_static_critical | 3 | 3 | 100.00 | |||
| rom_e2e_static_critical | 3947.660s | 16700.893us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_debug_cable_irq | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.167s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.167s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc | 6 | 6 | 100.00 | |||
| chip_sw_aes_enc | 277.360s | 3336.097us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 273.510s | 3282.934us | 3 | 3 | 100.00 | |
| chip_sw_aes_entropy | 3 | 3 | 100.00 | |||
| chip_sw_aes_entropy | 260.540s | 3091.261us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 3 | 3 | 100.00 | |||
| chip_sw_aes_idle | 212.040s | 3369.772us | 3 | 3 | 100.00 | |
| chip_sw_aes_sideload | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 2167.800s | 12856.259us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_alerts | 0 | 3 | 0.00 | |||
| chip_sw_alert_test | 241.030s | 3306.683us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_escalations | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 493.280s | 4953.601us | 3 | 3 | 100.00 | |
| chip_sw_all_escalation_resets | 89 | 100 | 89.00 | |||
| chip_sw_all_escalation_resets | 646.610s | 5796.762us | 89 | 100 | 89.00 | |
| chip_sw_alert_handler_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 820.990s | 5419.938us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 357.960s | 3905.735us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 560.350s | 4658.239us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_entropy | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_entropy | 241.800s | 3225.632us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_crashdump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1650.320s | 13746.834us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_timeout | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 401.540s | 4125.281us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 90 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 267.010s | 3498.983us | 0 | 90 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 14400.167s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1643.540s | 9688.650us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1336.980s | 7681.997us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_ok | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_ok | 1066.100s | 8057.789us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 13565.820s | 255210.480us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 341.640s | 4535.298us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_smoketest | 419.980s | 5516.061us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 341.640s | 4535.298us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 2 | 3 | 66.67 | |||
| chip_sw_aon_timer_wdog_bite_reset | 783.660s | 8769.992us | 2 | 3 | 66.67 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 2 | 3 | 66.67 | |||
| chip_sw_aon_timer_wdog_bite_reset | 783.660s | 8769.992us | 2 | 3 | 66.67 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 5 | 5 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 490.550s | 8366.939us | 5 | 5 | 100.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 489.490s | 5316.598us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 12 | 12 | 100.00 | |||
| chip_sw_otbn_randomness | 749.620s | 6010.383us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 212.040s | 3369.772us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_idle | 230.580s | 2548.078us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 184.380s | 3305.080us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_trans | 12 | 12 | 100.00 | |||
| chip_sw_clkmgr_off_aes_trans | 392.460s | 4218.593us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_hmac_trans | 443.010s | 5307.057us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_kmac_trans | 374.270s | 5364.230us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_otbn_trans | 411.910s | 5365.597us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_peri | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_off_peri | 1296.630s | 13277.532us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_div | 21 | 21 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 514.780s | 4323.091us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 511.830s | 4989.748us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 583.480s | 4973.064us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 539.420s | 5029.991us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 514.620s | 4477.044us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 516.690s | 4283.729us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_outputs | 779.650s | 8663.055us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_lc | 522.690s | 6660.225us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw | 6 | 6 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 583.480s | 4973.064us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 539.420s | 5029.991us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 448.430s | 4697.617us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 806.860s | 5876.907us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4633.540s | 19030.581us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 273.510s | 3282.934us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 1029.920s | 8705.852us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 257.970s | 3252.687us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 990.780s | 6013.655us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 246.360s | 3236.216us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 454.120s | 4771.830us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 233.290s | 3145.382us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_extended_range | 32 | 33 | 96.97 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 168.310s | 3568.669us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 514.460s | 5221.189us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 933.410s | 7650.628us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 4639.500s | 25228.654us | 2 | 3 | 66.67 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 246.140s | 2785.437us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 263.680s | 3555.210us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 936.660s | 7801.168us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 248.000s | 3832.414us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 549.800s | 6003.922us | 3 | 3 | 100.00 | |
| chip_sw_flash_init_reduced_freq | 1659.630s | 22460.264us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 3776.470s | 23832.140us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 779.650s | 8663.055us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_sleep_frequency | 511.560s | 5346.507us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_reset_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_reset_frequency | 377.410s | 3726.539us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_escalation_reset | 89 | 100 | 89.00 | |||
| chip_sw_all_escalation_resets | 646.610s | 5796.762us | 89 | 100 | 89.00 | |
| chip_sw_clkmgr_alert_handler_clock_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1643.540s | 9688.650us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_cmd | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3093.740s | 24329.842us | 3 | 3 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 1 | 3 | 33.33 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 432.580s | 5769.699us | 1 | 3 | 33.33 | |
| chip_sw_csrng_lc_hw_debug_en | 3 | 3 | 100.00 | |||
| chip_sw_csrng_lc_hw_debug_en_test | 590.920s | 6344.808us | 3 | 3 | 100.00 | |
| chip_sw_csrng_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_csrng_kat_test | 229.390s | 3333.737us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 16 | 16 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 7812.370s | 36110.952us | 10 | 10 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 222.700s | 2711.254us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 934.380s | 7453.452us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_ast_rng_req | 222.700s | 2711.254us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_csrng | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3093.740s | 24329.842us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_kat_test | 221.340s | 2692.397us | 3 | 3 | 100.00 | |
| chip_sw_flash_init | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1512.270s | 19435.072us | 3 | 3 | 100.00 | |
| chip_sw_flash_host_access | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_access | 745.140s | 5621.530us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 806.860s | 5876.907us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_ops | 487.230s | 3820.133us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en | 448.430s | 4697.617us | 3 | 3 | 100.00 | |
| chip_sw_flash_rma_unlocked | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4844.090s | 43124.050us | 3 | 3 | 100.00 | |
| chip_sw_flash_scramble | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1512.270s | 19435.072us | 3 | 3 | 100.00 | |
| chip_sw_flash_idle_low_power | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_idle_low_power | 316.330s | 3368.541us | 3 | 3 | 100.00 | |
| chip_sw_flash_keymgr_seeds | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2032.570s | 12997.362us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_creator_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 226.420s | 2452.717us | 0 | 3 | 0.00 | |
| chip_sw_flash_creator_seed_wipe_on_rma | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4844.090s | 43124.050us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_owner_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 226.420s | 2452.717us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 226.420s | 2452.717us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_wr_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 226.420s | 2452.717us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_seed_hw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 226.420s | 2452.717us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_escalate_en | 89 | 100 | 89.00 | |||
| chip_sw_all_escalation_resets | 646.610s | 5796.762us | 89 | 100 | 89.00 | |
| chip_sw_flash_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 260.380s | 8050.136us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_clock_freqs | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_clock_freqs | 721.290s | 5489.645us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_escalation_reset | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 582.850s | 5812.238us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_write_clear | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 582.850s | 5812.238us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc | 6 | 6 | 100.00 | |||
| chip_sw_hmac_enc | 270.370s | 3056.745us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 257.970s | 3252.687us | 3 | 3 | 100.00 | |
| chip_sw_hmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_hmac_enc_idle | 230.580s | 2548.078us | 3 | 3 | 100.00 | |
| chip_sw_hmac_all_configurations | 3 | 3 | 100.00 | |||
| chip_sw_hmac_oneshot | 1588.090s | 8851.490us | 3 | 3 | 100.00 | |
| chip_sw_hmac_multistream_mode | 3 | 3 | 100.00 | |||
| chip_sw_hmac_multistream | 954.790s | 5726.165us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx | 9 | 9 | 100.00 | |||
| chip_sw_i2c_host_tx_rx | 599.300s | 5442.339us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx1 | 530.420s | 5311.525us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx2 | 652.330s | 6591.169us | 3 | 3 | 100.00 | |
| chip_sw_i2c_device_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_i2c_device_tx_rx | 464.320s | 4363.595us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 6 | 6 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2032.570s | 12997.362us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 990.780s | 6013.655us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_kmac | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_kmac | 2367.560s | 13684.936us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_aes | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 2167.800s | 12856.259us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_otbn | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_otbn | 3475.910s | 13782.993us | 3 | 3 | 100.00 | |
| chip_sw_kmac_enc | 9 | 9 | 100.00 | |||
| chip_sw_kmac_mode_cshake | 252.610s | 2973.805us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac | 275.450s | 2695.436us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 246.360s | 3236.216us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_keymgr | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2032.570s | 12997.362us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_lc | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 741.880s | 9363.333us | 15 | 15 | 100.00 | |
| chip_sw_kmac_app_rom | 3 | 3 | 100.00 | |||
| chip_sw_kmac_app_rom | 249.950s | 3406.756us | 3 | 3 | 100.00 | |
| chip_sw_kmac_entropy | 3 | 3 | 100.00 | |||
| chip_sw_kmac_entropy | 1864.070s | 11149.587us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_kmac_idle | 184.380s | 3305.080us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 493.280s | 4953.601us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_jtag_access | 15 | 15 | 100.00 | |||
| chip_tap_straps_dev | 1603.450s | 15811.960us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 861.480s | 10747.611us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 516.850s | 7666.774us | 5 | 5 | 100.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 184.070s | 3350.936us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_init | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 741.880s | 9363.333us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_transitions | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 741.880s | 9363.333us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_kmac_req | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 741.880s | 9363.333us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_key_div | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation_prod | 2210.360s | 13244.366us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_broadcast | 76 | 84 | 90.48 | |||
| chip_sw_flash_ctrl_lc_rw_en | 226.420s | 2452.717us | 0 | 3 | 0.00 | |
| chip_sw_flash_rma_unlocked | 4844.090s | 43124.050us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 268.870s | 3046.746us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 751.330s | 6033.532us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 841.950s | 8612.553us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 666.110s | 6658.522us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 741.880s | 9363.333us | 15 | 15 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2032.570s | 12997.362us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 478.950s | 9569.827us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_execution_main | 792.770s | 7635.997us | 3 | 3 | 100.00 | |
| chip_prim_tl_access | 260.380s | 8050.136us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 522.690s | 6660.225us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 514.780s | 4323.091us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 511.830s | 4989.748us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 583.480s | 4973.064us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 539.420s | 5029.991us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 514.620s | 4477.044us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 516.690s | 4283.729us | 3 | 3 | 100.00 | |
| chip_tap_straps_dev | 1603.450s | 15811.960us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 861.480s | 10747.611us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 516.850s | 7666.774us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 299.030s | 8058.609us | 1 | 3 | 33.33 | |
| chip_lc_scrap | 6 | 6 | 100.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 193.290s | 3095.492us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 148.180s | 3558.996us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 126.390s | 2791.936us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 197.080s | 4272.080us | 3 | 3 | 100.00 | |
| chip_lc_test_locked | 4 | 6 | 66.67 | |||
| chip_sw_lc_walkthrough_testunlocks | 2192.750s | 31034.904us | 3 | 3 | 100.00 | |
| chip_rv_dm_lc_disabled | 299.030s | 8058.609us | 1 | 3 | 33.33 | |
| chip_sw_lc_walkthrough | 6 | 15 | 40.00 | |||
| chip_sw_lc_walkthrough_dev | 807.150s | 9015.239us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 928.160s | 11887.400us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 888.870s | 9271.133us | 3 | 3 | 100.00 | |
| chip_sw_lc_walkthrough_rma | 653.730s | 7339.844us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 2192.750s | 31034.904us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 6 | 9 | 66.67 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 100.330s | 2200.015us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 104.220s | 2341.727us | 3 | 3 | 100.00 | |
| rom_volatile_raw_unlock | 114.186s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_op | 6 | 6 | 100.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 4424.520s | 17747.338us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4633.540s | 19030.581us | 3 | 3 | 100.00 | |
| chip_sw_otbn_rnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 749.620s | 6010.383us | 3 | 3 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 749.620s | 6010.383us | 3 | 3 | 100.00 | |
| chip_sw_otbn_idle | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 749.620s | 6010.383us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 3 | 3 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 393.840s | 4121.386us | 3 | 3 | 100.00 | |
| chip_otp_ctrl_init | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 741.880s | 9363.333us | 15 | 15 | 100.00 | |
| chip_sw_otp_ctrl_keys | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1512.270s | 19435.072us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 393.840s | 4121.386us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2032.570s | 12997.362us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 458.570s | 3753.539us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 210.050s | 3032.609us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1512.270s | 19435.072us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 393.840s | 4121.386us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2032.570s | 12997.362us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 458.570s | 3753.539us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 210.050s | 3032.609us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_program | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 741.880s | 9363.333us | 15 | 15 | 100.00 | |
| chip_sw_otp_ctrl_program_error | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_program_error | 412.100s | 5379.424us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 184.070s | 3350.936us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals | 27 | 30 | 90.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 268.870s | 3046.746us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 751.330s | 6033.532us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 841.950s | 8612.553us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 666.110s | 6658.522us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 741.880s | 9363.333us | 15 | 15 | 100.00 | |
| chip_prim_tl_access | 260.380s | 8050.136us | 3 | 3 | 100.00 | |
| chip_sw_otp_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 260.380s | 8050.136us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_dai_lock | 1 | 1 | 100.00 | |||
| chip_sw_otp_ctrl_dai_lock | 1033.270s | 7724.028us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 255.580s | 5815.732us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 1370.050s | 26533.181us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 400.070s | 8151.424us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_por_reset | 2 | 3 | 66.67 | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 627.900s | 7963.398us | 2 | 3 | 66.67 | |
| chip_sw_pwrmgr_normal_sleep_por_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_por_reset | 592.210s | 6528.876us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 1223.040s | 26288.036us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 4 | 6 | 66.67 | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 1402.270s | 13723.783us | 2 | 3 | 66.67 | |
| chip_sw_aon_timer_wdog_bite_reset | 783.660s | 8769.992us | 2 | 3 | 66.67 | |
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 1284.910s | 10251.732us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_wdog_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_wdog_reset | 522.710s | 5600.770us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 255.580s | 5815.732us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 359.360s | 3852.116us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1 | 3 | 33.33 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 2763.650s | 35659.573us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 396.120s | 7272.287us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 213.560s | 3095.940us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1 | 3 | 33.33 | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1708.390s | 21207.588us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 909.370s | 8049.199us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_all_reset_reqs | 1341.070s | 11006.314us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_b2b_sleep_reset_req | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 2537.940s | 28824.443us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_disabled | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 265.010s | 3288.135us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_escalation_reset | 89 | 100 | 89.00 | |||
| chip_sw_all_escalation_resets | 646.610s | 5796.762us | 89 | 100 | 89.00 | |
| chip_sw_rom_access | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 478.950s | 9569.827us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 478.950s | 9569.827us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_non_sys_reset_info | 10 | 12 | 83.33 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1341.070s | 11006.314us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1708.390s | 21207.588us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_wdog_reset | 522.710s | 5600.770us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 419.980s | 5516.061us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sys_reset_info | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 362.000s | 4017.800us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 631.150s | 5681.128us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_req_reset | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 348.020s | 4872.853us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_alert_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1650.320s | 13746.834us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_rst | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 237.240s | 3275.577us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 89 | 100 | 89.00 | |||
| chip_sw_all_escalation_resets | 646.610s | 5796.762us | 89 | 100 | 89.00 | |
| chip_sw_rstmgr_alert_handler_reset_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1336.980s | 7681.997us | 3 | 3 | 100.00 | |
| chip_sw_nmi_irq | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 655.660s | 4719.927us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_rnd | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 675.230s | 4989.391us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 262.070s | 3102.108us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 210.050s | 3032.609us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 631.150s | 5681.128us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_double_fault | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 631.150s | 5681.128us | 3 | 3 | 100.00 | |
| chip_jtag_csr_rw | 3 | 3 | 100.00 | |||
| chip_jtag_csr_rw | 1831.180s | 18519.490us | 3 | 3 | 100.00 | |
| chip_jtag_mem_access | 3 | 3 | 100.00 | |||
| chip_jtag_mem_access | 1159.360s | 13897.729us | 3 | 3 | 100.00 | |
| chip_rv_dm_ndm_reset_req | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 362.000s | 4017.800us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 272.560s | 3412.778us | 0 | 3 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 387.830s | 6453.331us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_jtag_tap_sel | 5 | 5 | 100.00 | |||
| chip_tap_straps_rma | 861.480s | 10747.611us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 1 | 3 | 33.33 | |||
| chip_rv_dm_lc_disabled | 299.030s | 8058.609us | 1 | 3 | 33.33 | |
| chip_sw_plic_all_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 820.990s | 5419.938us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 357.960s | 3905.735us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 560.350s | 4658.239us | 3 | 3 | 100.00 | |
| chip_sw_plic_sw_irq | 3 | 3 | 100.00 | |||
| chip_sw_plic_sw_irq | 251.620s | 3453.772us | 3 | 3 | 100.00 | |
| chip_sw_timer | 3 | 3 | 100.00 | |||
| chip_sw_rv_timer_irq | 273.700s | 3349.366us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_flash_mode | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3704.390s | 15454.634us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pass_through | 672.870s | 7677.697us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 295.880s | 3542.699us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_tpm | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_tpm | 264.980s | 3508.957us | 3 | 3 | 100.00 | |
| chip_sw_spi_host_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_spi_host_tx_rx | 317.060s | 3383.533us | 3 | 3 | 100.00 | |
| chip_sw_sram_scrambled_access | 6 | 6 | 100.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 458.570s | 3753.539us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 454.120s | 4771.830us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents | 6 | 6 | 100.00 | |||
| chip_sw_sleep_sram_ret_contents_no_scramble | 724.470s | 8277.756us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents_scramble | 678.410s | 9867.554us | 3 | 3 | 100.00 | |
| chip_sw_sram_execution | 3 | 3 | 100.00 | |||
| chip_sw_sram_ctrl_execution_main | 792.770s | 7635.997us | 3 | 3 | 100.00 | |
| chip_sw_sram_lc_escalation | 95 | 106 | 89.62 | |||
| chip_sw_all_escalation_resets | 646.610s | 5796.762us | 89 | 100 | 89.00 | |
| chip_sw_data_integrity_escalation | 582.090s | 6107.439us | 6 | 6 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 4 | 6 | 66.67 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 909.370s | 8049.199us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 1501.460s | 23880.690us | 1 | 3 | 33.33 | |
| chip_sw_sysrst_ctrl_inputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_inputs | 250.150s | 3037.344us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_outputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_outputs | 269.690s | 3950.393us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_in_irq | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_in_irq | 456.780s | 4957.845us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_wakeup | 1 | 3 | 33.33 | |||
| chip_sw_sysrst_ctrl_reset | 1501.460s | 23880.690us | 1 | 3 | 33.33 | |
| chip_sw_sysrst_ctrl_sleep_reset | 1 | 3 | 33.33 | |||
| chip_sw_sysrst_ctrl_reset | 1501.460s | 23880.690us | 1 | 3 | 33.33 | |
| chip_sw_sysrst_ctrl_ec_rst_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3137.880s | 21117.444us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_flash_wp_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3137.880s | 21117.444us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 3 | 6 | 50.00 | |||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 368.560s | 5342.734us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.167s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_usbdev_vbus | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_vbus | 176.670s | 2714.938us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pullup | 277.080s | 3203.515us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_aon_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_aon_pullup | 360.190s | 3342.081us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_setup_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_setuprx | 395.440s | 4431.823us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_config_host | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_config_host | 1303.100s | 7852.419us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pincfg | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pincfg | 6535.500s | 31597.638us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_tx_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_dpi | 2333.470s | 12700.114us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_toggle_restore | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_toggle_restore | 159.620s | 2430.034us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 3 | 3 | 100.00 | |||
| chip_sw_aes_masking_off | 271.020s | 3156.191us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 242.200s | 2945.005us | 3 | 3 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_coremark | 1 | 1 | 100.00 | |||
| chip_sw_coremark | 16594.570s | 72147.778us | 1 | 1 | 100.00 | |
| chip_sw_power_max_load | 3 | 3 | 100.00 | |||
| chip_sw_power_virus | 1360.370s | 6757.278us | 3 | 3 | 100.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 160.170s | 4571.130us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 798.120s | 14447.489us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 606.020s | 14024.901us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 68.235s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 32.512s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 20.310s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 3 | 0.00 | |||
| rom_e2e_self_hash | 193.781s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter_cycle_measurements | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter_frequency | 375.930s | 3899.846us | 0 | 3 | 0.00 | |
| chip_sw_edn_boot_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_boot_mode | 525.920s | 3306.956us | 3 | 3 | 100.00 | |
| chip_sw_edn_auto_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_auto_mode | 1389.220s | 6311.355us | 3 | 3 | 100.00 | |
| chip_sw_edn_sw_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_sw_mode | 1970.430s | 10724.403us | 3 | 3 | 100.00 | |
| chip_sw_edn_kat | 3 | 3 | 100.00 | |||
| chip_sw_edn_kat | 322.870s | 2930.957us | 3 | 3 | 100.00 | |
| chip_sw_flash_memory_protection | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_mem_protection | 767.880s | 5216.654us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 154.780s | 2234.560us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 210.270s | 3115.844us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_deep_sleep_wake_up | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 414.100s | 5494.682us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 496.350s | 5369.831us | 3 | 3 | 100.00 | |
| chip_sw_all_resets | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1341.070s | 11006.314us | 3 | 3 | 100.00 | |
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 160.170s | 4571.130us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 798.120s | 14447.489us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 606.020s | 14024.901us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 488.100s | 5891.616us | 3 | 3 | 100.00 | |
| chip_sw_plic_alerts | 89 | 100 | 89.00 | |||
| chip_sw_all_escalation_resets | 646.610s | 5796.762us | 89 | 100 | 89.00 | |
| tick_configuration | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.206s | 0.000us | 0 | 3 | 0.00 | |
| counter_wrap | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.206s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_output_when_disabled_or_sleeping | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pinmux_sleep_retention | 223.510s | 3693.114us | 3 | 3 | 100.00 | |
| chip_sw_uart_watermarks | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 531.240s | 4727.122us | 5 | 5 | 100.00 | |
| chip_sw_usbdev_stream | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_stream | 4349.330s | 19526.273us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 18 | 28 | 64.29 | |||
| chip_sival_flash_info_access | 257.470s | 3210.276us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 585.460s | 5838.513us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_rot_auth_config | 7.710s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_ecc_error_vendor_test | 220.200s | 3085.227us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_descrambling | 256.800s | 2578.909us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_lowpower_cancel | 337.440s | 4090.634us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sleep_wake_5_bug | 16.490s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 257.580s | 3362.558us | 3 | 3 | 100.00 | |
| ate_bootstrap_flash_erase | 9521.460s | 45295.929us | 3 | 3 | 100.00 | |
| ate_bootstrap_disjoint | 10800.165s | 0.000us | 0 | 3 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) | 90 test runs | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 73772211106781938617289692328544247699398598054575044666190054997761047507388 | 308 |
UVM_INFO @ 2883.704973 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90200047054677266325083024838310150444414843278817438664419948660970712177426 | 308 |
UVM_INFO @ 3162.190535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 63948726406036663870122695824798224977832451979850662502042410545443941551700 | 308 |
UVM_INFO @ 3015.818570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 14482615212046936297254353576183346675398504854446155475252260850336126185486 | 308 |
UVM_INFO @ 3288.328036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90112758053365605576688766326095826746536066527741560712850703355842107884341 | 308 |
UVM_INFO @ 2897.566104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81683418703377123577913949425517311933379834757546554262134074124564070010105 | 308 |
UVM_INFO @ 3078.634676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3210348881633723484217178675119891333562573028918402486399802629629340990786 | 313 |
UVM_INFO @ 2218.726565 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 30092824681001389984318202788591574172766758030240554974023049032589453275892 | 308 |
UVM_INFO @ 2967.244040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 20759993194041726527556556765333209413018597289391076067464124858753190481623 | 308 |
UVM_INFO @ 3531.643277 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 82195371249969345532069861258793228328530203456743581580394832790855580782560 | 308 |
UVM_INFO @ 3518.106700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 21154303393955983141119899085564523815811678295410084957745337750308970988715 | 308 |
UVM_INFO @ 3318.574730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 51508558212031144163427415640242432655127278072508989556851419211625583607231 | 308 |
UVM_INFO @ 3514.285850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 40942686807904308161559834826427356595117348967973976911917355681312104704111 | 308 |
UVM_INFO @ 3127.561565 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50681623210081627995150575880701777371664217386374671544155777123712998457144 | 308 |
UVM_INFO @ 3036.742803 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 34976663125895056714684508358398040058938781599084910366610121209237823370210 | 308 |
UVM_INFO @ 2357.087530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 55841543503402521149952349855946351008142518031147024279527566450217106885447 | 308 |
UVM_INFO @ 2652.995925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 53492011552638904129828932369579522801494496234722157128567503533082125342913 | 308 |
UVM_INFO @ 3507.158013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 2953513741839361489137117334581763853303128260886138807455827295212172340881 | 308 |
UVM_INFO @ 3253.633204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 9645173933977011122509735544542684353912098526051495421409524414352955485984 | 308 |
UVM_INFO @ 3467.369194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 73579517533209164162288238396015207481559929692975730884045190014289819933414 | 308 |
UVM_INFO @ 3072.486176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1607185098224780469178120290683868385163028015002018707247476908798920042670 | 308 |
UVM_INFO @ 2647.687804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 98386290904003016597128798852509104000913170610813574643984987533483552498968 | 308 |
UVM_INFO @ 2336.061448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99479747813185140370983130610279983508946457899045230961324245092532380298829 | 308 |
UVM_INFO @ 2903.622344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97094873027175459879242106723633813556433675214543868821689698577625680517272 | 308 |
UVM_INFO @ 3348.600398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3207416537087078697457859634766451684274625702896029941098696384826858243115 | 308 |
UVM_INFO @ 3236.000408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 11564056706798692249963268135041042538726179332311561127588458728661243903806 | 308 |
UVM_INFO @ 2746.375742 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 73958304668401180558922279593363308165225795108067733950854241193438262788579 | 308 |
UVM_INFO @ 2778.524232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 6458127032964887558658570339017408928939137940274482071225686793204608018023 | 308 |
UVM_INFO @ 3001.326630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 6843416348117348853761645417530126513850219102583779948012886990116023091850 | 308 |
UVM_INFO @ 2956.782912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 16957842454939569658214386731921771823086767514116558890084351615136921466861 | 308 |
UVM_INFO @ 3158.489552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 37771504988816467688565334321800187404535068370995776419481036233146481967893 | 308 |
UVM_INFO @ 2538.425508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 102544922329217902709013227761059313719817840701451573943677886687649028553623 | 308 |
UVM_INFO @ 3202.266902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 36642251619986449829717162567672652521048463517898261197431267736468790277058 | 308 |
UVM_INFO @ 2367.143612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 53900774338333835469245812985815729047187266144006476418968981731928545423820 | 308 |
UVM_INFO @ 2771.304761 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93376827310146274929353519567187919782209822257799637309550877832988397769616 | 308 |
UVM_INFO @ 3183.255600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97557997360884378909222181056794031609274631801736220656309156845612861978297 | 308 |
UVM_INFO @ 3151.012847 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 67202869111673319594642874228752409749520324006482473191526617236626859512028 | 308 |
UVM_INFO @ 3202.821912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 74239690208853492677861031478688613272073209391412503667793107770284563410959 | 308 |
UVM_INFO @ 3388.894264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 105803660977352463356745202243559483577460247132949442108333190295189870583417 | 308 |
UVM_INFO @ 2461.775091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 74723323209214002225594204962123127965795919633725594659227176715239668265651 | 308 |
UVM_INFO @ 2847.353450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 107415349069769498128287607152247272785045792963147165406751645448803095700857 | 308 |
UVM_INFO @ 2790.160207 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 67410548224888028220091525070657376533870380874274065470597605683978139644700 | 308 |
UVM_INFO @ 2902.916328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 18282387246876834636815906285594879245761260767126791093627009266529855190726 | 308 |
UVM_INFO @ 2797.648829 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96779726659224844354990384157432762991866640720321058381081731735324462475354 | 308 |
UVM_INFO @ 3205.608936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 53539242535311977980140476468380876590875112294130329059608815831167394975828 | 308 |
UVM_INFO @ 3654.019033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 31852309876433747313858576968632531570321391764923992852945648543719335021486 | 308 |
UVM_INFO @ 3242.198713 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65879965050474295851955059921765488449590275045702669452618015806688766208048 | 308 |
UVM_INFO @ 2875.914220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 56746007705749306063405085965868113939237586376645108340853160470715021131601 | 308 |
UVM_INFO @ 2694.835254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 57602119849798610109982543308101391487135478548755112030222815771310413296214 | 308 |
UVM_INFO @ 2708.408560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90867406711932412605403895190525447134716158984052220154948481266762643164677 | 308 |
UVM_INFO @ 3348.511456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 67003759002583999607833996431206953544740350905533296061841783216765660641144 | 308 |
UVM_INFO @ 3399.431750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 70274050579454126409602132783821799683009711500396372719678266842051771503899 | 308 |
UVM_INFO @ 3101.221556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 15599553262912195314857408311957355913443477531706487894866247302950490224571 | 308 |
UVM_INFO @ 2379.214703 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 69489921420526037662605593638645592651462034171989865288347418746780145450740 | 308 |
UVM_INFO @ 2768.044076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 14960203309054569870171580985773749554214783589398290386074867559539677590428 | 313 |
UVM_INFO @ 3286.941480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 95970148024414847269731970605413875364109058070647915104150522067433427885183 | 313 |
UVM_INFO @ 3291.379630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 24835624447506601119819287174546593765750402039254863479564788754560708767256 | 313 |
UVM_INFO @ 3058.172445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 10344284113763434386931087678749223829006160042055455149597452383037714312555 | 313 |
UVM_INFO @ 2498.850563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 34490158481140838672931365358734344176158315058519383419228560399637239961782 | 313 |
UVM_INFO @ 3053.897336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93203832094687283944260296691785178974739529572545486953559455547613586071448 | 313 |
UVM_INFO @ 3405.275445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96801701632188391459942054437524624493155564205881212920472560973623179679231 | 313 |
UVM_INFO @ 3104.722376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 51051043304947777766878660405258845381517574367818467789549294812908633284983 | 308 |
UVM_INFO @ 2786.519371 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3226678267845336385685807385401545848668356991682211842620023906397478012376 | 308 |
UVM_INFO @ 2973.066595 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 101062901633734362683456003064791770247096526939252175058593535953904427550709 | 308 |
UVM_INFO @ 2879.422888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 51794456005119134443578091575669203771339125809631129790136229937028133285655 | 308 |
UVM_INFO @ 2818.616215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 92265461959686029945054105120597807997077541680643360345654189360800780400537 | 308 |
UVM_INFO @ 2842.864120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 48220806378376990305576924390305400564564276627238594271751526084313670160009 | 308 |
UVM_INFO @ 2399.997852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 72298524974497834473741667584540219378645640200299333444639078297444368002275 | 308 |
UVM_INFO @ 2796.994111 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65488738255185778667329538607454135925096495306274681253288465024796537358183 | 308 |
UVM_INFO @ 3432.109895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 88852874512668777777722251369110642152048764021221211071014870578091695927812 | 308 |
UVM_INFO @ 2665.447280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 17995956308293208911673063481564391655383341805234155923714070779132997216975 | 308 |
UVM_INFO @ 2897.142915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 111506843339763021135575221356752348321218603942758463164188093701007385185912 | 308 |
UVM_INFO @ 2959.830594 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 112807324683723695808352497461951886369277487768451804778948126757163239326768 | 308 |
UVM_INFO @ 3121.586622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 89879336401309488615528288434031386525517178446948732927847149658666202901891 | 308 |
UVM_INFO @ 2806.178608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 75447896317819966312784312960764283026576852562310019164185465595275705512631 | 308 |
UVM_INFO @ 3007.638095 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65815104472993924540208155736485998335014623374477759210644281090097307644106 | 308 |
UVM_INFO @ 2470.510100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 71757610046882027733823120845821997608514280210636830790430784216562351435664 | 308 |
UVM_INFO @ 3001.220194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 112332570107594034916677299990461896222932708344322278253665630034453864674146 | 308 |
UVM_INFO @ 2726.833250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 104137625393702720081861418954978186776286051014691721766162175148952531831825 | 308 |
UVM_INFO @ 2994.513750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 107407019673840964963629659073802554539494545524122777104341509449361543664591 | 308 |
UVM_INFO @ 2468.975408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 27837347812958263659929023240018668291420358674770769974786566568390872429053 | 308 |
UVM_INFO @ 2819.081884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 25180583933321487760015576884794390077866872867694474027209479089766104195364 | 308 |
UVM_INFO @ 3024.827588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 63182322822986045065933337384863706703726831606671370627777570981113072922215 | 308 |
UVM_INFO @ 3500.419064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 17447354068319978331633570603413121524969904394597457817073120739221637517734 | 308 |
UVM_INFO @ 2629.089064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97236037600033666081793855212096952562058004353904508380857040579548193171658 | 308 |
UVM_INFO @ 3498.982608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 57629244953899999486521602076121350012784729068586471719129772107395595048474 | 308 |
UVM_INFO @ 3273.018182 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 113980469044459776521432216100535052038775703823005024313625611291533616236398 | 308 |
UVM_INFO @ 3088.612459 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 19881461274246332459754967326373882337380103993165867707912843047603984635500 | 308 |
UVM_INFO @ 3270.622064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 111752837097952107086469633100739040662505307905267095916812048747095173640791 | 308 |
UVM_INFO @ 2656.245610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 11471631270782362754339112289808431985025633234484232036459001306512984008515 | 308 |
UVM_INFO @ 3412.123743 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 61 test runs | |||
| chip_sw_pwrmgr_sleep_wake_5_bug | 2711930170351367091069002221919918723708824110054898621703328632646569008709 | None |
---- STDERR ----
Another command (pid=3057681) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 80210045064878890085877562020024077585184642985841324332395504898870478316956 | None |
Another command (pid=353209) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=362219) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=359536) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 17737335896274807192510598273751388823743943471038316142058582091882056674788 | None |
Another command (pid=282119) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=273303) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=280932) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 9429430713012157655722663683401796366374256714877952159822744447891699697505 | None |
Another command (pid=280630) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=316734) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=278889) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 100855246406220595086976703078852831442803910415609063258466923202358963327256 | None |
Another command (pid=263937) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=263761) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=281952) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 21040450728073304284831750370466105915872741316426756547855436804854230933621 | None |
---- STDERR ----
Another command (pid=279421) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=280235) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 82172682604016758213086364358740642510403792302495031704913470788364596080028 | None |
Another command (pid=264390) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=268193) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=265076) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 90095344709107730530749545677003796569578746423225114581253490022352738294625 | None |
Another command (pid=317815) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=318651) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=316653) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 72141429703054254414402072107798040917888402850467922464152970864359973615439 | None |
---- STDERR ----
Another command (pid=279421) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=280235) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 9015652345011492178159627941527067692504989237288989190956377758870552439002 | None |
Another command (pid=308951) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=275645) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=273703) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 109492031160814436662543252612800935875812165694025909385533316583181055101324 | None |
Another command (pid=341870) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=338363) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=319119) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 9676362560372692332287713670624417201172394175132205848708403318461738856724 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 78463899844254033881046518266122310644185181809477047740245671295423137594196 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 55036885861134180775866653440579752800233487216244803478016619839552933223425 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 109208526373124979541702391073520135172072585724149607492750959006273700533043 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 33496653489173116699719444438387628539610994742073652041667593663790024343855 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 34553875311308640702696257454673193002362827946489582661511431558986809735686 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 34402239960631065961919357553579182145123828539439805086774745959575879928263 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 78240731363587694149951927349684250794280612861792014064444242182171310059140 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 15056976811267732484880643638149790902511300272180870835555344037337323060711 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 113937200101483790410064735886307181631044270821142128607765631981284780667116 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 6144680761389141019135627841569710700649544761335958433298847989049301685431 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 2399202610345197535460627954686481928565504282249953478673746967137044616628 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 22714832357337591412465376180521366147464382133304595760593961665701622391445 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 92616646066175678219158940314262453212352139742942416419625086376512972224627 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 54264628449377033511807338710831572311705960662657499600219278023897154875609 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 42664564727668882394083615242357982756687489241489335733392911812463032134265 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 34465608893447900749788897437430563420550395289652576931926593270841199931765 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 67681644884775833524611168567234730996017986189151800779616642982162375260656 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 98500789982511303647478770547146932467087702889377547477087173370651976077385 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 36468800074703636209439697859111937201288845712314159425916927835238436122871 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 115696894189052231712836296063979368422473270569488401839622763739247089987553 | None |
Waiting for it to complete...
Another command (pid=263759) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 108435597760776032172336832385064529317694936190399907372249054344170331745321 | None |
Another command (pid=338518) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=331064) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=317252) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 4240875337769296004617666822605609613971997420468081535398207280747186883448 | None |
Another command (pid=264390) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=266563) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=268193) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 73885179021030643835963624615106339646292595720111575105473999887555083123057 | None |
Another command (pid=379923) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=384523) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=272104) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 60621392366987847396698445008247258679993001979191882422484402811473527027363 | None |
Another command (pid=265025) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=274065) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=277061) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 66867046923551579598873098350376242266090955567551905273959194778911387129557 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_dev | 98820022120446653737804760385910696549926431166236880879475876376793351094958 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_rma | 61109825600291166445927050085006992817263529859678453905581398708364494621843 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 43911495713547912450691665360642938730349758786611423796579518133994474789927 | None |
Another command (pid=263759) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=267669) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=268520) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 3738024941230834056841764495233550274950842474113787240335525545751289194339 | None |
Another command (pid=311049) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=269965) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=321811) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 63752329628654249572940118269310848996190760652348179725448066145167342645190 | None |
Another command (pid=272908) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=279421) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=280235) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 52798484382073224208689490534396460547102992759317353070575601824836449261950 | None |
---- STDERR ----
Another command (pid=3976456) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 13783200446536749855628147554862853473234246088730581086007066670238538929492 | None |
---- STDERR ----
Another command (pid=263759) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 73022879239863490382532117264442044905056349181361052877760312962780937628986 | None |
---- STDERR ----
Another command (pid=279421) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=280235) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 76640325864486213807759533147115562719831527403384929316406619536253778282364 | None |
Another command (pid=301896) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=282119) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=273303) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 62740947781868626635251034995798006736703581554705188248782853752563869781529 | None |
Another command (pid=275645) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=267342) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=290564) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 1569328782648034552211790584201763964600358728770780358449111853470924277103 | None |
Another command (pid=379923) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=384523) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=272104) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 76239731133781791459931345762755803230600725401484851580567621840874280968274 | None |
Another command (pid=268340) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=272758) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=275092) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 44673194105409158710039440994347964886066681588721473838470318589367943320906 | None |
Another command (pid=263759) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=267669) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=268520) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 15240913421686745540695424484795888378788136449906326607803040547707619792503 | None |
Another command (pid=267129) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=267070) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=264390) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 22748779012658141654868668323202509313301575235208340007087365441360676036626 | None |
Another command (pid=723900) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=721119) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=725869) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 46786437208862377834026835092226779962380182180243748237784136306290570168462 | None |
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:otbn_ecdsa_op_irq_test_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
---- STDOUT ----
---- STDERR ----
2026/05/08 15:06:43 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
_run_cmd -> had a non-zero return code of 36.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 40732335285894079793917746086725862732899656823410245230232401868905281419065 | None |
Another command (pid=272511) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=268193) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=265076) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 20718862791203648834560283039481329511182081629554254769187563469589177475312 | None |
Another command (pid=388672) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=391859) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=334881) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 36034445113961759026771115419292338289297099567521218816173330516039058300718 | None |
---- STDERR ----
Another command (pid=273519) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=275645) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 58779189421260754980546186991838265494365301808540464663082588211744545535927 | None |
Another command (pid=418350) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=394764) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=306619) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 34508147922195532910193752691738717047434866715027998375927745954574546178832 | None |
Another command (pid=313212) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=315257) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=321253) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 66904904337116669176549687925814049508349160869856600709435418078459879141313 | None |
Another command (pid=274065) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=272758) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=276078) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 107284649369445684900518967957061071250120085621691956384269095408309921962760 | None |
---- STDERR ----
Another command (pid=263759) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 57799577659607225605073216495614142645553586433983129664564434383159961456418 | None |
Another command (pid=273519) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=308951) is running. Waiting for it to complete on the server (server_pid=263778)...
Another command (pid=275645) is running. Waiting for it to complete on the server (server_pid=263778)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). | 32 test runs | |||
| chip_tl_errors | 60341339271123580781269052888977937796565519828203729902282836320725632270137 | 217 |
TL item was: req: (cip_tl_seq_item@31485) { a_addr: 'h1075c a_data: 'h2bc82cf6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1f a_opcode: 'h4 a_user: 'h18d93 d_param: 'h0 d_source: 'h1f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2240.641342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 83441406973613205904819861269630924024013198399764136189872181367034736777182 | 242 |
TL item was: req: (cip_tl_seq_item@217575) { a_addr: 'h105a0 a_data: 'hf6f0accd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h1baef d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 6045.244760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 93914349001868702435101994849178741485206843343946666503808574959584046083806 | 217 |
TL item was: req: (cip_tl_seq_item@34435) { a_addr: 'h10510 a_data: 'h8edbab9f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h1b617 d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2246.064688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 62445975720561232142909622196733640242991754891034772380494458976727516640458 | 224 |
TL item was: req: (cip_tl_seq_item@31563) { a_addr: 'h10660 a_data: 'hec91d297 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h1ae92 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1992.389604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 17406545010014396383344191638611067182623649710562344423542954877761327612124 | 217 |
TL item was: req: (cip_tl_seq_item@43775) { a_addr: 'h10454 a_data: 'h2f62d79b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h25 a_opcode: 'h4 a_user: 'h1952d d_param: 'h0 d_source: 'h25 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3131.105541 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 9526817952585830514693461803703207605999869079102840610274239990820004446131 | 224 |
TL item was: req: (cip_tl_seq_item@32209) { a_addr: 'h1035c a_data: 'h2778fc90 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h19e9c d_param: 'h0 d_source: 'h35 d_data: 'h100073 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd04 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2179.669576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 86843368195354089914811381650349970566541801406943983127077917664915143386533 | 217 |
TL item was: req: (cip_tl_seq_item@37383) { a_addr: 'h107fc a_data: 'h78f60038 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1a5a2 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1773.375500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 27177671817942426067241814822941095905025276684785730738101655796331548271888 | 224 |
TL item was: req: (cip_tl_seq_item@31881) { a_addr: 'h10538 a_data: 'hf1ffb178 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h1ba0c d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2116.817543 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 89826490368226485928091550824347786902920539996224224442956285447458059146956 | 217 |
TL item was: req: (cip_tl_seq_item@33017) { a_addr: 'h10640 a_data: 'h4589bf8e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1b628 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2240.494188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 73200877355750090959197667629557276622917240802586572665786009856729744252009 | 224 |
TL item was: req: (cip_tl_seq_item@31525) { a_addr: 'h107f4 a_data: 'hc4d2f685 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h1b108 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1703.708971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 18585685818755563035960824652885365506536164680244830117785644698988866919602 | 217 |
TL item was: req: (cip_tl_seq_item@39943) { a_addr: 'h1052c a_data: 'he356a13d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h19250 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2328.712609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 97793680618159594359401095281368184034304877613335191269668441720868385093012 | 217 |
TL item was: req: (cip_tl_seq_item@33803) { a_addr: 'h105a0 a_data: 'h9f8654b4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1ba82 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2136.222598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 111968332034167417667337629399711462323754859357979865092968177098084065511058 | 217 |
TL item was: req: (cip_tl_seq_item@32491) { a_addr: 'h104a0 a_data: 'h9fee676c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h1bd8f d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2318.284970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 5240011680249229647249251724357516934792607415799593435332977681397142081771 | 217 |
TL item was: req: (cip_tl_seq_item@31555) { a_addr: 'h10770 a_data: 'hc157b588 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h18d55 d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1872.730016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 73334930210913715848784443742955995676950767843990685486297901973417015136726 | 218 |
TL item was: req: (cip_tl_seq_item@193507) { a_addr: 'h107d0 a_data: 'hc489831f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1a53d d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3021.526668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 47779831142063949615594575992868810903123947709488481011340043637149805417647 | 217 |
TL item was: req: (cip_tl_seq_item@42129) { a_addr: 'h10358 a_data: 'h6537fc07 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h19207 d_param: 'h0 d_source: 'h18 d_data: 'h7b302573 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd1f a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2824.101800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 99439410421278231213294506379298061955660061542030610123665138762375799712603 | 217 |
TL item was: req: (cip_tl_seq_item@31465) { a_addr: 'h104e4 a_data: 'h7e75e09 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2b a_opcode: 'h4 a_user: 'h199a0 d_param: 'h0 d_source: 'h2b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2512.829745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 93189186752568110124550660432997588884810388794577877378448138410918323498246 | 217 |
TL item was: req: (cip_tl_seq_item@32859) { a_addr: 'h105f4 a_data: 'ha54d8f9d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h1ba15 d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2066.510934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 56600199253196105613831605703290093064375967957801308770340734310335290831348 | 217 |
TL item was: req: (cip_tl_seq_item@32365) { a_addr: 'h10348 a_data: 'hc2a3293f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h1b6b8 d_param: 'h0 d_source: 'h28 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2787.571873 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 1967950907336582688529687636673910846496839086304743735434769004572532259851 | 217 |
TL item was: req: (cip_tl_seq_item@35469) { a_addr: 'h10718 a_data: 'h334fe34a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h1a9fb d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1939.050417 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 54450767518265641971830634229120536998760280929508233538256293146910648700587 | 218 |
TL item was: req: (cip_tl_seq_item@94611) { a_addr: 'h10518 a_data: 'hfda61e96 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h1a2bc d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2862.456989 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 97761778507830626831214733413676082735935757736456653649678772223283033734458 | 218 |
TL item was: req: (cip_tl_seq_item@138227) { a_addr: 'h105f4 a_data: 'h3bf5de51 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h1ba4c d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3295.576660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 43064069293129935165329256361090572581458611017445499937726224780902463233016 | 217 |
TL item was: req: (cip_tl_seq_item@33561) { a_addr: 'h107cc a_data: 'h98f0d0cc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h37 a_opcode: 'h4 a_user: 'h199d7 d_param: 'h0 d_source: 'h37 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1685.652370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 79203107922541170651051428086069689850782849384590196824558354812444659450513 | 217 |
TL item was: req: (cip_tl_seq_item@31615) { a_addr: 'h1035c a_data: 'h717ce642 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h19e99 d_param: 'h0 d_source: 'h29 d_data: 'h100073 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd04 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2099.638851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 70195587897169260868677797277970844865112996206858824731111900115570904610298 | 218 |
TL item was: req: (cip_tl_seq_item@414817) { a_addr: 'h10774 a_data: 'h546f367e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h1818a d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 4529.644500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 76773566794959597985534074176341959873046122383575173048943749820840333431135 | 217 |
TL item was: req: (cip_tl_seq_item@32245) { a_addr: 'h10728 a_data: 'h838b87ae a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h195af d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2432.146408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 80958082196777916221704040598626875152869392519244331153930629420518480548536 | 217 |
TL item was: req: (cip_tl_seq_item@32023) { a_addr: 'h106e0 a_data: 'h6d4c6bc9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h19e69 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2161.743875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 11612300366989863669196785268428424440273397716928039032076615984667894670402 | 217 |
TL item was: req: (cip_tl_seq_item@33521) { a_addr: 'h104b8 a_data: 'h466f36bc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h18de1 d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2182.932776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 96008471505689316692559295764527671699344399211386407437335065396763488887551 | 217 |
TL item was: req: (cip_tl_seq_item@32757) { a_addr: 'h104c4 a_data: 'h6f62196e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2f a_opcode: 'h4 a_user: 'h18139 d_param: 'h0 d_source: 'h2f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2279.749019 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 68088296741265296675702989567040195199085187888014414773214125901078670085032 | 217 |
TL item was: req: (cip_tl_seq_item@33251) { a_addr: 'h10448 a_data: 'h3ea1b756 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h1a9ed d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2983.364840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 80266437332251820954464221411104468593742091345143975298446906698971928792383 | 217 |
TL item was: req: (cip_tl_seq_item@32461) { a_addr: 'h1045c a_data: 'h46c98612 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h22 a_opcode: 'h4 a_user: 'h181cc d_param: 'h0 d_source: 'h22 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2892.045650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 60406351341232751065510596740520816779425928439647664748123982689468658071432 | 217 |
TL item was: req: (cip_tl_seq_item@34051) { a_addr: 'h106c8 a_data: 'hc9100818 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h22 a_opcode: 'h4 a_user: 'h19245 d_param: 'h0 d_source: 'h22 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2274.477486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 12 test runs | |||
| chip_sw_rv_timer_systick_test | 1398116187252619426249751128826084561901145358230814906793934635006338097563 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 80997004483972567782138039561982821985430894117698482625586949576914588913653 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 48768538371112550409328945411701403572607945590498818199277521600932158893338 | None | ||
| ate_bootstrap_disjoint | 70704995040519917735721716236707022979411370566811386337643134774655413896663 | None | ||
| chip_sw_rv_timer_systick_test | 100421236556922409141252895665713483621955423693497254001481849458158483407743 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 8508614837529202172831425026148785585516434980325721397213454315512494853739 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 12398909623144099857900027703038813732968028882137359908977653730409872355601 | None | ||
| ate_bootstrap_disjoint | 10866131826298121016685557572779574506360218701393432036947854936482938213430 | None | ||
| chip_sw_rv_timer_systick_test | 50503430586022318148923537100726088648587370298650155565316681427100791070307 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 78435216543886856058736631259824983058421617435437973834373535883679135927538 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 3464610984473149394134733744866692494168112304104405703233017920640798184500 | None | ||
| ate_bootstrap_disjoint | 51408036175346737557326133569737787097201596428232999483881817817230525515999 | None | ||
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 9 test runs | |||
| chip_sw_lc_walkthrough_dev | 108668273377617605500609969324179709406487006318658635993794170997660089020214 | 369 |
UVM_INFO @ 9015.238516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 102492312300769104689521698186272842880265311982599544169540993951260834604582 | 369 |
UVM_INFO @ 11887.400374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 34471144952211452635329261733905329135964987160546203823153407514984844811096 | 341 |
UVM_INFO @ 6829.637040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 113427677037469933997097010133045153428034312828745497889253089870094873435226 | 369 |
UVM_INFO @ 11994.553854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 13763466744130242152657855006324975335502318556439882925817814701937507067703 | 369 |
UVM_INFO @ 11123.019195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 21209184868576436149948471154213580405702297465125369654392830275421831277966 | 341 |
UVM_INFO @ 7339.844364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 34908536369675089986847311763975208609698748050979450672415298369672960725370 | 369 |
UVM_INFO @ 9007.471280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 62463122646814358509315250105151165549424586759984249577481371838593177611886 | 369 |
UVM_INFO @ 8759.005080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 61661309979441149570854713555632639778570716281136070271362995695223311234543 | 341 |
UVM_INFO @ 7012.176950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(rstreqs[*] && (reset_cause == HwReq))' | 9 test runs | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 66111319122170463039264344016299750658434060577164027751244560486666509481625 | 325 |
UVM_ERROR @ 7213.482000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7213.482000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 88450034596511024834812359870832129336493002964186513595029365759841496858981 | 329 |
UVM_ERROR @ 8016.068000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8016.068000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sysrst_ctrl_reset | 20142212247475847368643283739373909770487063418008577717362401393267229888285 | 334 |
UVM_ERROR @ 23880.690000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23880.690000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 57801469089956432399793929525616419823716708072133608581154151253665008657175 | 344 |
UVM_ERROR @ 13156.947500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13156.947500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 7001251048615161619335892116092935752383313489758841441701596843133548612482 | 314 |
UVM_ERROR @ 5166.494000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5166.494000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sysrst_ctrl_reset | 20968977814684012541542942268445316922212012274016206285485408671798114326344 | 334 |
UVM_ERROR @ 23592.947500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23592.947500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 4566068303529432578245359048601702804808598187699866887881064131357847112066 | 344 |
UVM_ERROR @ 14064.800500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 14064.800500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 57077376218068640806705502497381108845650113236279307707798871137575795685897 | 391 |
UVM_ERROR @ 17873.292000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 17873.292000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 81556167090405427978750012712434828043560296656995935463737900307028454957065 | 319 |
UVM_ERROR @ 7389.647000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7389.647000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 7 test runs | |||
| chip_sw_otp_ctrl_escalation | 20228495389597229712815391649259051945796760533350119241964421065615097592790 | 316 |
UVM_ERROR @ 3115.843536 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3115.843536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 31227986750731411836721752882998235568883026059084855505309692260101481159626 | 312 |
UVM_ERROR @ 2132.016152 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2132.016152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 71735812920652775266014353321262078547649702027689206783023411098451216818169 | 312 |
UVM_ERROR @ 3058.374480 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3058.374480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 37212203546963348510515215953602861882816884826054235057463749364258473700192 | 317 |
UVM_ERROR @ 2752.886624 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2752.886624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 71445370440626829049981673105560265669566996400424979550462433318663859038381 | 317 |
UVM_ERROR @ 2790.799020 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2790.799020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 31979322196182453790012359819020742289967724233760095076290718327209418625021 | 317 |
UVM_ERROR @ 2964.567392 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2964.567392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 17589755213775656808304948600121891567281616849716528516485375172468834861886 | 317 |
UVM_ERROR @ 2754.581470 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2754.581470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault | 5 test runs | |||
| chip_sw_all_escalation_resets | 111473149454241941739560779272669888448910966343467405045374005307072898101567 | 316 |
UVM_INFO @ 2664.418316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 104468045788497599399812554329615775365664540563074233862489009287070801360957 | 316 |
UVM_INFO @ 2753.508472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 75847502050556037626178788571919441096806294000003478192817195254745423772070 | 316 |
UVM_INFO @ 2747.691648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 51169117381171854337247386244972645831855742279193959303487468488429507249788 | 316 |
UVM_INFO @ 2961.573090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 114649813282981328479958559256194753012210991852891469638205315898526745564682 | 316 |
UVM_INFO @ 3141.656684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Error-[NOA] Null object access | 4 test runs | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 3617921126856918117205034830276696913710097098058285254788185280710327706413 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 63533206290116966229246727268811979178174060962942003200805746208441511347907 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 71027640845281945450887504065876274514425983647390236645982020754570524701514 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 104372201267960053962750155384562791892905809814794779155597468174709341332039 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] | 3 test runs | |||
| chip_sw_sleep_pin_mio_dio_val | 90781385276443935397701392401402776249852250610745636986338722775915722724545 | 451 |
UVM_INFO @ 3576.390500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sleep_pin_mio_dio_val | 113338928127831181610261085602963069596101845542648241416365418120148820952055 | 451 |
UVM_INFO @ 2831.475000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sleep_pin_mio_dio_val | 35813836591529239689491880065317218155069651990144362419336767551069056950409 | 451 |
UVM_INFO @ 2881.602500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 3 test runs | |||
| chip_sw_spi_device_pass_through_collision | 79425629434239032495977166862271475913011012177397648111037246417597544903422 | 320 |
UVM_INFO @ 3391.045012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 32625860885051219669304099251070172517802240136928333076530426593386769519102 | 320 |
UVM_INFO @ 3542.698520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 99774629640658391891886815214535956908231685261179372004022707316163912678815 | 320 |
UVM_INFO @ 3099.074879 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_flash_ctrl_lc_rw_en | 111447467084161691836214269474491383809124279233812098997766032872955720981114 | 309 |
UVM_INFO @ 3025.772950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 18480348555289683290579801482542813934699857268580424484550482382766874566257 | 309 |
UVM_INFO @ 3173.924156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 8573659242009415767026170337082114694811347101127100582341849214138412869281 | 309 |
UVM_INFO @ 2452.717423 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * | 3 test runs | |||
| chip_sw_otp_ctrl_lc_signals_rma | 43203232332657005468767244376610934468239643102825469823622203213707858718096 | 342 |
UVM_INFO @ 6316.770269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 93633105003782419259303750072138973126732337634301469670562264235064110666382 | 342 |
UVM_INFO @ 7012.570698 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 74302196082081218831341921746271153201351061054753034095848253099548949452232 | 342 |
UVM_INFO @ 6658.521605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((~rst_ni) === (~seed_en_q))' | 3 test runs | |||
| chip_sw_pwrmgr_full_aon_reset | 52429188263414247221724202940950506656007336043210662339068617976334744694993 | 316 |
UVM_ERROR @ 5815.731720 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5815.731720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 75202435998740351669490005564492927919883171304919218412082568653256478071459 | 318 |
UVM_ERROR @ 5703.334840 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5703.334840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 4324613330491754216080646803851759069808357159567968523634492988179984536029 | 303 |
UVM_ERROR @ 2492.794715 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2492.794715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' | 3 test runs | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 62486400712983007882448474022815359090556921173309749454712039972476291555628 | 313 |
UVM_ERROR @ 3095.939570 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3095.939570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 36521860630683400287691464823524164780037518140092020464801230916132818328093 | 313 |
UVM_ERROR @ 3079.433477 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3079.433477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 55135026040913526824067057157317118240607530181414972072432187992390928584512 | 313 |
UVM_ERROR @ 3267.970947 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3267.970947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_clkmgr_jitter_frequency | 44181787331619062139011221932265231032563582598378999754944316676299638422018 | 343 |
UVM_INFO @ 3301.801603 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 35501096908664771845921900555030907325734994724982667791518407065565839069067 | 343 |
UVM_INFO @ 3899.846494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 61129306241413242219872667062376194601832426407879390340809821417714416200547 | 343 |
UVM_INFO @ 3343.852237 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() | 3 test runs | |||
| chip_sw_pwrmgr_lowpower_cancel | 41589013334246134527121967302183635157212151097715897802841929808693789362488 | 317 |
UVM_INFO @ 4090.634292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_lowpower_cancel | 71601828653440875963745654109345014518871745368667402096134653076495204482332 | 317 |
UVM_INFO @ 3388.912567 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_lowpower_cancel | 77796015186287336088349903552406394987748654677895063582267758694159655124402 | 317 |
UVM_INFO @ 3413.125647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_idle_load | 29376167009681407314761910736412449577117011383733388816896839693134053654420 | 312 |
UVM_INFO @ 3103.125000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 51786034229705334724743479103086614037356776617957419336884352952113332684012 | 314 |
UVM_INFO @ 3325.520000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 55871783056446491791387875847715397424769761604880498844373362442381051481539 | 312 |
UVM_INFO @ 2487.126000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_sleep_load | 3662912112737831916644317831055112037947473064359229278343636256952588282754 | 318 |
UVM_INFO @ 3548.079000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 11816942857531698980432815348204325825813435654842192588554534870371606866823 | 318 |
UVM_INFO @ 3591.562000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 8467720783594976464625162843729791240936741274157526160144059068297587017931 | 318 |
UVM_INFO @ 3107.225000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * | 3 test runs | |||
| chip_sw_ast_clk_rst_inputs | 10186495706836260868913058313657811784193350939873371948569315768594371440051 | 327 |
UVM_INFO @ 9599.000977 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 104100379399755810013850741782160427134445485924572493978225069885012152790860 | 327 |
UVM_INFO @ 10825.461428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 33674803817353037071207429035706446562576835145364592803376984632989634655781 | 327 |
UVM_INFO @ 13614.684153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '$stable(key_data_i)' | 3 test runs | |||
| rom_keymgr_functest | 74240697763083441223954450241515431134859493467788830833367088317290164816663 | 327 |
UVM_ERROR @ 5699.101310 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5699.101310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 35186941267739419643730476889540522291429031787230725694741653877790213809426 | 327 |
UVM_ERROR @ 4389.898303 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4389.898303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 50008597305957761446702735405653721412530868451135999120215600661510158900399 | 327 |
UVM_ERROR @ 4756.992063 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4756.992063 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 2 test runs | |||
| chip_rv_dm_lc_disabled | 31440904049428809222130507217337796074129265777493361033288551455594295310430 | 215 |
UVM_INFO @ 2340.356102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 106434365272312343706968269680681830292128065057265086624034835230012089731080 | 267 |
UVM_INFO @ 8058.609195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! | 2 test runs | |||
| rom_e2e_jtag_debug_dev | 25594488952092655876347174290245538930855838783996518126627114945504972977142 | 330 |
UVM_INFO @ 14447.489320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_jtag_debug_rma | 44732865253619831703541954216684014806305565133163694659159197686319722161471 | 330 |
UVM_INFO @ 14024.900782 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 2 test runs | |||
| rom_e2e_keymgr_init_rom_ext_meas | 10778602311951706578163878249539748641159894100524266899597528861534403680215 | 319 |
UVM_INFO @ 15712.728512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_keymgr_init_rom_ext_meas | 61228553495761842767530618719401802934354772757145965083292965905656469290901 | 319 |
UVM_INFO @ 16730.877209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * | 2 test runs | |||
| chip_sw_all_escalation_resets | 13083619938515496284722110850737229322089086076030951305339630109491847021465 | 317 |
UVM_INFO @ 3592.699008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 46173634880502949000000424811056642323107084253197245754779860843634687349345 | 317 |
UVM_INFO @ 3036.597964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_otp_ctrl_rot_auth_config | 46952344915656734251504652848872082593562635241983973712843179563412660295377 | 282 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 47324062528000329167090574282863915965953221894524633853252070082275533462996 | 307 |
UVM_INFO @ 2837.245005 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 38859118079644364931256521594323787554023448477500067373600576639490822658361 | 307 |
UVM_INFO @ 3034.431254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(pend_req[h2d.a_source].pend == *)' | 1 test run | |||
| rom_e2e_shutdown_output | 105298090992157655882285444261221496443253520732615856481338852311858356365195 | 307 |
UVM_ERROR @ 2476.185795 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 2476.185795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 10989382823638385268110254492834526734274234644496257668530954704340073275328 | 307 |
UVM_INFO @ 3306.683192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 1 test run | |||
| rom_e2e_keymgr_init_rom_ext_no_meas | 1239497685038331652195594386659653023300567862669295423969719893275739316861 | 319 |
UVM_INFO @ 16943.591504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|