Simulation Results: clkmgr

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.39 %
  • code
  • 98.89 %
  • assert
  • 96.47 %
  • func
  • 87.82 %
  • line
  • 99.33 %
  • branch
  • 99.15 %
  • cond
  • 95.98 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.89%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.260s 40.961us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.950s 17.777us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.700s 205.934us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 8.000s 2038.148us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.500s 143.427us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.960s 138.631us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.700s 205.934us 5 5 100.00
clkmgr_csr_aliasing 2.500s 143.427us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.190s 45.553us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.810s 222.533us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.600s 129.818us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.550s 157.178us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.260s 40.961us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 9.130s 1806.279us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 8.830s 2197.124us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 9.130s 1806.279us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 88.150s 13921.475us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.330s 80.168us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
clkmgr_tl_errors 2.910s 215.380us 5 5 100.00
tl_d_illegal_access 5 5 100.00
clkmgr_tl_errors 2.910s 215.380us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 0.950s 17.777us 1 1 100.00
clkmgr_csr_rw 1.700s 205.934us 5 5 100.00
clkmgr_csr_aliasing 2.500s 143.427us 1 1 100.00
clkmgr_same_csr_outstanding 2.320s 298.659us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 0.950s 17.777us 1 1 100.00
clkmgr_csr_rw 1.700s 205.934us 5 5 100.00
clkmgr_csr_aliasing 2.500s 143.427us 1 1 100.00
clkmgr_same_csr_outstanding 2.320s 298.659us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 8 10 80.00
clkmgr_sec_cm 3.890s 656.712us 3 5 60.00
clkmgr_tl_intg_err 3.440s 704.843us 5 5 100.00
shadow_reg_update_error 5 5 100.00
clkmgr_shadow_reg_errors 4.340s 883.187us 5 5 100.00
shadow_reg_read_clear_staged_value 5 5 100.00
clkmgr_shadow_reg_errors 4.340s 883.187us 5 5 100.00
shadow_reg_storage_error 5 5 100.00
clkmgr_shadow_reg_errors 4.340s 883.187us 5 5 100.00
shadowed_reset_glitch 5 5 100.00
clkmgr_shadow_reg_errors 4.340s 883.187us 5 5 100.00
shadow_reg_update_error_with_csr_rw 5 5 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.470s 394.845us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
clkmgr_tl_intg_err 3.440s 704.843us 5 5 100.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 9.130s 1806.279us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 8.830s 2197.124us 10 10 100.00
sec_cm_meas_config_shadow 5 5 100.00
clkmgr_shadow_reg_errors 4.340s 883.187us 5 5 100.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.380s 49.303us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.450s 79.703us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.420s 79.618us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_clk_handshake_intersig_mubi 1.730s 189.671us 10 10 100.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.220s 147.514us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.700s 205.934us 5 5 100.00
sec_cm_idle_ctr_redun 3 5 60.00
clkmgr_sec_cm 3.890s 656.712us 3 5 60.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.700s 205.934us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.700s 205.934us 5 5 100.00
prim_count_check 3 5 60.00
clkmgr_sec_cm 3.890s 656.712us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 5.690s 974.635us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 79.650s 14936.654us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
clkmgr_sec_cm 92427390343489492522036693344801949273219412725670120060305422511674171241896 83
UVM_INFO @ 9234400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 8717440238370291803801769433123716231175846744346890001985562904489619530479 77
UVM_INFO @ 3197007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---