Simulation Results: csrng

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.57 %
  • code
  • 96.23 %
  • assert
  • 95.85 %
  • func
  • 88.63 %
  • block
  • 98.59 %
  • line
  • 99.57 %
  • branch
  • 96.46 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.28%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
csrng_smoke 33.000s 20.445us 10 10 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 33.000s 29.097us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 33.000s 21.583us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 38.000s 108.791us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 37.000s 167.165us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 34.000s 103.804us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 33.000s 21.583us 5 5 100.00
csrng_csr_aliasing 37.000s 167.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
alerts 500 500 100.00
csrng_alert 43.000s 3477.230us 500 500 100.00
err 500 500 100.00
csrng_err 33.000s 34.489us 500 500 100.00
cmds 1 10 10.00
csrng_cmds 56.000s 2367.999us 1 10 10.00
life cycle 1 10 10.00
csrng_cmds 56.000s 2367.999us 1 10 10.00
stress_all 10 10 100.00
csrng_stress_all 188.000s 4475.365us 10 10 100.00
intr_test 10 10 100.00
csrng_intr_test 33.000s 27.924us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 33.000s 43.749us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
csrng_tl_errors 31.000s 43.800us 5 5 100.00
tl_d_illegal_access 5 5 100.00
csrng_tl_errors 31.000s 43.800us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 33.000s 29.097us 1 1 100.00
csrng_csr_rw 33.000s 21.583us 5 5 100.00
csrng_csr_aliasing 37.000s 167.165us 1 1 100.00
csrng_same_csr_outstanding 34.000s 93.526us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 33.000s 29.097us 1 1 100.00
csrng_csr_rw 33.000s 21.583us 5 5 100.00
csrng_csr_aliasing 37.000s 167.165us 1 1 100.00
csrng_same_csr_outstanding 34.000s 93.526us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
csrng_sec_cm 34.000s 55.254us 5 5 100.00
csrng_tl_intg_err 28.000s 126.380us 5 5 100.00
sec_cm_config_regwen 15 15 100.00
csrng_regwen 33.000s 25.941us 10 10 100.00
csrng_csr_rw 33.000s 21.583us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 43.000s 3477.230us 500 500 100.00
sec_cm_intersig_mubi 10 10 100.00
csrng_stress_all 188.000s 4475.365us 10 10 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
csrng_sec_cm 34.000s 55.254us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
csrng_sec_cm 34.000s 55.254us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
csrng_sec_cm 34.000s 55.254us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
csrng_sec_cm 34.000s 55.254us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
csrng_sec_cm 34.000s 55.254us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 43.000s 3477.230us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
sec_cm_constants_lc_gated 10 10 100.00
csrng_stress_all 188.000s 4475.365us 10 10 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 43.000s 3477.230us 500 500 100.00
sec_cm_tile_link_bus_integrity 5 5 100.00
csrng_tl_intg_err 28.000s 126.380us 5 5 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
csrng_sec_cm 34.000s 55.254us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
csrng_sec_cm 34.000s 55.254us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 36.000s 181.951us 200 200 100.00
csrng_err 33.000s 34.489us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 10802.149s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
csrng_stress_all_with_rand_reset 97564870072097694017800563812209999809517292498816332933558733380688270573829 None
csrng_stress_all_with_rand_reset 35704031210214843901155785377280750581740789224423833608358138380788385209188 None
csrng_stress_all_with_rand_reset 12181972347261855487953187684119418377541991559423214939257574881413460886104 None
csrng_stress_all_with_rand_reset 38311519657480083665483085650177090943484763676944111045760723135978599356720 None
csrng_stress_all_with_rand_reset 81320974172896276184200440584186165726398999387829566799373883567203508426780 None
csrng_stress_all_with_rand_reset 91770624212437212028602765575916009410723615591657172738337233704234651877200 None
csrng_stress_all_with_rand_reset 14258423907488810063059575053167902050514659238230109924518628052387267827611 None
csrng_stress_all_with_rand_reset 10603967762278336049652445272606227643536592986001050321237866376957063179069 None
csrng_stress_all_with_rand_reset 102414115001101805417541769568513368388256576950382260530563140155144559315573 None
csrng_stress_all_with_rand_reset 3589015931865083638502934967653846495629855244864638977344853569869490641339 None
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 8 test runs
csrng_cmds 62883755951892250360009907532403123308368725415760414660476755329586554812596 130
UVM_INFO @ 275741779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 49025439216261585356739356362970568424182021254342219443156111012457278533031 130
UVM_INFO @ 112951768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 80505726030117200338029645719580622020148658762097887485823889555553718577274 130
UVM_INFO @ 166559748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 98891778593888738673637874933092480858752637458238642408301094540238902513145 140
UVM_INFO @ 185875142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 3369515360131328010968840001188375292359010851289335318072772054531084818168 130
UVM_INFO @ 82131548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 21288978144048973772556019377742152549248927469617347461072542275880852808860 130
UVM_INFO @ 324059561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 5313375867022177214360533670398097995906229168067058069640258222004292609021 130
UVM_INFO @ 1361244945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 90423938711049571045082278926329784667062939851552551150433251819330177057682 130
UVM_INFO @ 159180574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 15317041509139794522624840174180747397701530483645123284422317874078619126820 139
UVM_INFO @ 15516721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---