Simulation Results: edn/edn0

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.84 %
  • code
  • 94.24 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 91.85 %
  • FSM
  • 89.78 %
Validation stages
V1
100.00%
V2
99.81%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 0.960s 20.288us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.040s 17.172us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.150s 50.889us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.600s 287.948us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 91.583us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.190s 115.848us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.150s 50.889us 5 5 100.00
edn_csr_aliasing 1.240s 91.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 3.210s 615.465us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 3.210s 615.465us 100 100 100.00
genbits 100 100 100.00
edn_genbits 3.210s 615.465us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.040s 38.159us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.300s 216.946us 200 200 100.00
errs 100 100 100.00
edn_err 1.240s 34.571us 100 100 100.00
disable 49 50 98.00
edn_disable 0.990s 16.576us 30 30 100.00
edn_disable_auto_req_mode 1.260s 39.006us 19 20 95.00
stress_all 10 10 100.00
edn_stress_all 4.810s 627.928us 10 10 100.00
intr_test 10 10 100.00
edn_intr_test 1.000s 25.380us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.390s 50.198us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
edn_tl_errors 2.530s 125.230us 5 5 100.00
tl_d_illegal_access 5 5 100.00
edn_tl_errors 2.530s 125.230us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.040s 17.172us 1 1 100.00
edn_csr_rw 1.150s 50.889us 5 5 100.00
edn_csr_aliasing 1.240s 91.583us 1 1 100.00
edn_same_csr_outstanding 1.270s 124.012us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.040s 17.172us 1 1 100.00
edn_csr_rw 1.150s 50.889us 5 5 100.00
edn_csr_aliasing 1.240s 91.583us 1 1 100.00
edn_same_csr_outstanding 1.270s 124.012us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
edn_sec_cm 11.340s 10571.777us 5 5 100.00
edn_tl_intg_err 2.600s 154.165us 5 5 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.100s 56.446us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.300s 216.946us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.340s 10571.777us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.340s 10571.777us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 11.340s 10571.777us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 11.340s 10571.777us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.300s 216.946us 200 200 100.00
edn_sec_cm 11.340s 10571.777us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.300s 216.946us 200 200 100.00
sec_cm_tile_link_bus_integrity 5 5 100.00
edn_tl_intg_err 2.600s 154.165us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 178.390s 104363.221us 26 30 86.67

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 25495992077119925050625101579844810854855701533123535329171157817571757416350 289
UVM_INFO @ 4501338306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 14625110578214682255844728367458499472086662282925198347188264432509244817023 256
UVM_INFO @ 2902107935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 90205469392146447968146648303568111606150111585453475574177252309458544313174 155
UVM_INFO @ 1091684295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 70550682972035663738910497504994346769393883803554076492244897844758173576113 270
UVM_INFO @ 3239415703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 54629530048358488000346316331123989319354516696420516365353209979537880996083 88
UVM_INFO @ 44109939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---