Simulation Results: edn/edn1

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.94 %
  • code
  • 95.45 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.85 %
  • toggle
  • 96.15 %
  • FSM
  • 93.18 %
Validation stages
V1
100.00%
V2
99.23%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 0.870s 17.764us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 59.903us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 0.790s 16.476us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.130s 1208.479us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.900s 15.165us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.130s 59.335us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 0.790s 16.476us 5 5 100.00
edn_csr_aliasing 0.900s 15.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 2.680s 280.861us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 2.680s 280.861us 100 100 100.00
genbits 100 100 100.00
edn_genbits 2.680s 280.861us 100 100 100.00
interrupts 20 20 100.00
edn_intr 0.950s 21.046us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.130s 105.180us 200 200 100.00
errs 100 100 100.00
edn_err 1.090s 22.080us 100 100 100.00
disable 46 50 92.00
edn_disable 0.840s 14.970us 30 30 100.00
edn_disable_auto_req_mode 8.070s 500.000us 16 20 80.00
stress_all 10 10 100.00
edn_stress_all 4.790s 210.154us 10 10 100.00
intr_test 10 10 100.00
edn_intr_test 0.840s 28.084us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 0.820s 45.280us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
edn_tl_errors 1.920s 300.224us 5 5 100.00
tl_d_illegal_access 5 5 100.00
edn_tl_errors 1.920s 300.224us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.810s 59.903us 1 1 100.00
edn_csr_rw 0.790s 16.476us 5 5 100.00
edn_csr_aliasing 0.900s 15.165us 1 1 100.00
edn_same_csr_outstanding 1.100s 41.811us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.810s 59.903us 1 1 100.00
edn_csr_rw 0.790s 16.476us 5 5 100.00
edn_csr_aliasing 0.900s 15.165us 1 1 100.00
edn_same_csr_outstanding 1.100s 41.811us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
edn_sec_cm 3.440s 1512.265us 5 5 100.00
edn_tl_intg_err 2.140s 268.405us 5 5 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 0.880s 18.595us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.130s 105.180us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.440s 1512.265us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.440s 1512.265us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.440s 1512.265us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.440s 1512.265us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.130s 105.180us 200 200 100.00
edn_sec_cm 3.440s 1512.265us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.130s 105.180us 200 200 100.00
sec_cm_tile_link_bus_integrity 5 5 100.00
edn_tl_intg_err 2.140s 268.405us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 130.660s 14732.923us 25 30 83.33

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 88025415977392608741497338778365107207988830277074386361480564707759792331945 174
UVM_INFO @ 2017640163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 89451621362632379019095332287135873648837114715656775453080811248727217152068 143
UVM_INFO @ 121300161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 64681820094578558482696251187397506371108012510180367753332361136291783981627 170
UVM_INFO @ 1191190315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 75183161947419486136358897713943570255506247910270524181563516876238854952791 122
UVM_INFO @ 355616349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
edn_disable_auto_req_mode 66182491170400571171247516166970636711219614297804687210962101567394960019226 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88247927712619920868344157458281686506176454681192377983673735744578663308467 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 53472634243219032011817757132123416138487496512851828378713325122981106485268 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
edn_stress_all_with_rand_reset 42158184146706387550565027050277029687702402852964023353898515634692965172958 135
UVM_INFO @ 1489788303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 66267032416324294243311105685528584990731293748998319674615637379994802379609 88
UVM_INFO @ 36182952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---