Simulation Results: flash_ctrl

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.94 %
  • code
  • 95.91 %
  • assert
  • 96.76 %
  • func
  • 98.14 %
  • line
  • 96.11 %
  • branch
  • 97.47 %
  • cond
  • 94.77 %
  • toggle
  • 98.66 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
98.57%
V2S
98.59%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 140.210s 99.358us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 23.930s 31.412us 5 5 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 17.640s 125.572us 1 1 100.00
csr_rw 5 5 100.00
flash_ctrl_csr_rw 16.600s 130.839us 5 5 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 45.800s 14906.197us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 26.710s 377.093us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 20.540s 107.614us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
flash_ctrl_csr_rw 16.600s 130.839us 5 5 100.00
flash_ctrl_csr_aliasing 26.710s 377.093us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 11.110s 17.734us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 11.110s 43.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 19.800s 31.220us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 106.530s 307.491us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1757.880s 340366.158us 3 3 100.00
flash_ctrl_hw_rma_reset 845.200s 160198.256us 20 20 100.00
flash_ctrl_lcmgr_intg 13.470s 48.856us 20 20 100.00
host_controller_arb 4 5 80.00
flash_ctrl_host_ctrl_arb 1635.910s 510559.590us 4 5 80.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 222.070s 1397.629us 5 5 100.00
program_reset 29 30 96.67
flash_ctrl_prog_reset 3604.012s 0.000us 29 30 96.67
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3434.610s 814869.733us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 77.990s 1509.937us 5 5 100.00
rd_buff_eviction_w_ecc 97 100 97.00
flash_ctrl_rw_evict 30.840s 38.917us 38 40 95.00
flash_ctrl_rw_evict_all_en 32.780s 41.780us 39 40 97.50
flash_ctrl_re_evict 34.580s 57.509us 20 20 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 254.720s 8453.187us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 254.720s 8453.187us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 752.690s 45621.842us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 25.630s 403.662us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 674.980s 141.223us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 588.160s 5305.317us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 472.030s 2891.402us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1508.230s 3097.485us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 13.490s 73.951us 20 20 100.00
read_write_overflow 4 5 80.00
flash_ctrl_oversize_error 3604.014s 0.000us 4 5 80.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 21.590s 64.440us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 17.350s 27.489us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 808.630s 1029.906us 5 5 100.00
secret_partition 128 130 98.46
flash_ctrl_hw_sec_otp 210.650s 85943.751us 50 50 100.00
flash_ctrl_otp_reset 133.790s 38.645us 78 80 97.50
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1757.880s 340366.158us 3 3 100.00
interrupts 98 100 98.00
flash_ctrl_intr_rd 197.200s 2747.894us 38 40 95.00
flash_ctrl_intr_wr 84.200s 37137.926us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 527.700s 151995.362us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 295.440s 157929.501us 10 10 100.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 82.100s 1802.856us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 64.920s 2209.903us 5 5 100.00
double_bit_err 35 35 100.00
flash_ctrl_read_word_sweep_derr 23.490s 59.041us 5 5 100.00
flash_ctrl_ro_derr 129.050s 804.701us 10 10 100.00
flash_ctrl_rw_derr 195.050s 4621.418us 10 10 100.00
flash_ctrl_derr_detect 143.500s 937.932us 5 5 100.00
flash_ctrl_integrity 524.750s 18629.721us 5 5 100.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 15.340s 86.641us 5 5 100.00
flash_ctrl_ro_serr 117.170s 5525.275us 10 10 100.00
flash_ctrl_rw_serr 223.310s 2320.682us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 82.580s 1209.633us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 69.230s 3189.612us 5 5 100.00
scramble 59 62 95.16
flash_ctrl_wo 229.630s 5636.996us 20 20 100.00
flash_ctrl_write_word_sweep 8.020s 215.663us 1 1 100.00
flash_ctrl_read_word_sweep 10.010s 49.719us 1 1 100.00
flash_ctrl_ro 109.170s 639.586us 20 20 100.00
flash_ctrl_rw 3604.014s 0.000us 17 20 85.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 34.830s 1265.562us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 754.430s 137108.319us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 289.660s 10020.240us 20 20 100.00
alert_test 10 10 100.00
flash_ctrl_alert_test 13.920s 82.505us 10 10 100.00
intr_test 10 10 100.00
flash_ctrl_intr_test 13.230s 25.266us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
flash_ctrl_tl_errors 18.850s 163.148us 5 5 100.00
tl_d_illegal_access 5 5 100.00
flash_ctrl_tl_errors 18.850s 163.148us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
flash_ctrl_csr_hw_reset 17.640s 125.572us 1 1 100.00
flash_ctrl_csr_rw 16.600s 130.839us 5 5 100.00
flash_ctrl_csr_aliasing 26.710s 377.093us 1 1 100.00
flash_ctrl_same_csr_outstanding 18.550s 133.601us 5 5 100.00
tl_d_partial_access 12 12 100.00
flash_ctrl_csr_hw_reset 17.640s 125.572us 1 1 100.00
flash_ctrl_csr_rw 16.600s 130.839us 5 5 100.00
flash_ctrl_csr_aliasing 26.710s 377.093us 1 1 100.00
flash_ctrl_same_csr_outstanding 18.550s 133.601us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 5 5 100.00
flash_ctrl_shadow_reg_errors 56.070s 222.671us 5 5 100.00
shadow_reg_read_clear_staged_value 5 5 100.00
flash_ctrl_shadow_reg_errors 56.070s 222.671us 5 5 100.00
shadow_reg_storage_error 5 5 100.00
flash_ctrl_shadow_reg_errors 56.070s 222.671us 5 5 100.00
shadowed_reset_glitch 5 5 100.00
flash_ctrl_shadow_reg_errors 56.070s 222.671us 5 5 100.00
shadow_reg_update_error_with_csr_rw 5 5 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 69.020s 1013.158us 5 5 100.00
tl_intg_err 10 10 100.00
flash_ctrl_sec_cm 2337.210s 2574.614us 5 5 100.00
flash_ctrl_tl_intg_err 675.240s 1966.144us 5 5 100.00
sec_cm_reg_bus_integrity 5 5 100.00
flash_ctrl_tl_intg_err 675.240s 1966.144us 5 5 100.00
sec_cm_host_bus_integrity 5 5 100.00
flash_ctrl_tl_intg_err 675.240s 1966.144us 5 5 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 27.370s 63.234us 3 3 100.00
flash_ctrl_wr_intg 13.870s 50.714us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 140.210s 99.358us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 258 260 99.23
flash_ctrl_otp_reset 133.790s 38.645us 78 80 97.50
flash_ctrl_disable 21.590s 64.440us 50 50 100.00
flash_ctrl_sec_info_access 77.100s 5124.178us 50 50 100.00
flash_ctrl_connect 17.350s 27.489us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 13.480s 38.177us 5 5 100.00
sec_cm_data_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.600s 130.839us 5 5 100.00
sec_cm_data_regions_config_shadow 5 5 100.00
flash_ctrl_shadow_reg_errors 56.070s 222.671us 5 5 100.00
sec_cm_info_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.600s 130.839us 5 5 100.00
sec_cm_info_regions_config_shadow 5 5 100.00
flash_ctrl_shadow_reg_errors 56.070s 222.671us 5 5 100.00
sec_cm_bank_config_regwen 5 5 100.00
flash_ctrl_csr_rw 16.600s 130.839us 5 5 100.00
sec_cm_bank_config_shadow 5 5 100.00
flash_ctrl_shadow_reg_errors 56.070s 222.671us 5 5 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 21.590s 64.440us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 27.370s 63.234us 3 3 100.00
flash_ctrl_access_after_disable 13.490s 43.010us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 14.680s 67.702us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 21.590s 64.440us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 25.630s 403.662us 10 10 100.00
sec_cm_mem_scramble 17 20 85.00
flash_ctrl_rw 3604.014s 0.000us 17 20 85.00
sec_cm_mem_integrity 25 25 100.00
flash_ctrl_rw_serr 223.310s 2320.682us 10 10 100.00
flash_ctrl_rw_derr 195.050s 4621.418us 10 10 100.00
flash_ctrl_integrity 524.750s 18629.721us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1757.880s 340366.158us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2337.210s 2574.614us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2337.210s 2574.614us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2337.210s 2574.614us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2337.210s 2574.614us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 21.630s 768.785us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 4 5 80.00
flash_ctrl_phy_host_grant_err 12.210s 22.825us 4 5 80.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 17.650s 147.381us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2337.210s 2574.614us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2337.210s 2574.614us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2337.210s 2574.614us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.790s 49.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 410.210s 1796.647us 3 3 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
flash_ctrl_rw 71994305147684530969181240946579905679286776288205043710815718232804029537352 None
flash_ctrl_oversize_error 76254625341223171095270026326695371444429496046269651100273410423944763744068 None
flash_ctrl_rw 109580961218903821504876858090874571839190330212612082102430808234073247451110 None
flash_ctrl_prog_reset 5781873922115933000121950802701034851254473710413284444957061258517082922023 None
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 2 test runs
flash_ctrl_rw_evict_all_en 65006428614996683107518421202647696809744373937187021006096979600338029600829 108
UVM_INFO @ 34996.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict 17816025740566859890253862713946942861441933444717494281381419619427504419425 108
UVM_INFO @ 67694.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q 2 test runs
flash_ctrl_otp_reset 79959413159596050005735842005013442310320793041100896372368365526358177526287 161
UVM_INFO @ 13346.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_otp_reset 73264131527312091653319199226616774969700628884202990349359769366902957440045 222
UVM_INFO @ 27601.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (* [*] vs * [*]) 1 test run
flash_ctrl_host_ctrl_arb 64813703781880914938514879713306362858934494320616946368521638296544798492464 236
UVM_INFO @ 78739243.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 1 test run
flash_ctrl_phy_host_grant_err 56691046826315311090658277053100679958053900348175313964494168836043989958215 125
UVM_ERROR @ 7551.0 ns: (alert_esc_if.sv:201) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 7551.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp e27011a6_1261287c:ffffffff_1261287c mismatch!! 1 test run
flash_ctrl_intr_rd 71143993555259592186061734678313707763844843089712438815713274268756736929851 108
UVM_INFO @ 842912.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly 1 test run
flash_ctrl_rw 38824250506181830164875252693832432252402099810328840368324208871463870514852 108
UVM_INFO @ 6047600.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *ce8f2c_2bbf1b16:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 12531591716594343897713544939697882431354783659367714738269214338279561192935 108
UVM_INFO @ 192960.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * 1 test run
flash_ctrl_rw_evict 37168922623986517633764167478322708499233941225902624185262852566145255446293 108
UVM_INFO @ 15102.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---