| V1 |
|
100.00% |
| V2 |
|
93.43% |
| V2S |
|
100.00% |
| V3 |
|
30.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 1.840s | 249.339us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.800s | 72.504us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.800s | 85.678us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.820s | 318.229us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.960s | 17.235us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 0.980s | 16.033us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 2.990s | 1608.742us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.160s | 70.013us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.280s | 27.527us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 0.980s | 16.033us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.160s | 70.013us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 1.620s | 339.613us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.770s | 229.155us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.290s | 171.990us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 1.700s | 305.087us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 3.220s | 349.588us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 4.270s | 93.915us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 33.570s | 4219.994us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 5.800s | 335.628us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.530s | 91.346us | 10 | 10 | 100.00 | |
| stress_all | 1 | 10 | 10.00 | |||
| gpio_stress_all | 55.520s | 20519.690us | 1 | 10 | 10.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.930s | 93.925us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 0.960s | 48.383us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 5 | 5 | 100.00 | |||
| gpio_tl_errors | 2.860s | 103.377us | 5 | 5 | 100.00 | |
| tl_d_illegal_access | 5 | 5 | 100.00 | |||
| gpio_tl_errors | 2.860s | 103.377us | 5 | 5 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| gpio_csr_rw | 0.980s | 16.033us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.250s | 40.368us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.160s | 70.013us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.960s | 17.235us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| gpio_csr_rw | 0.980s | 16.033us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.250s | 40.368us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.160s | 70.013us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.960s | 17.235us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 10 | 10 | 100.00 | |||
| gpio_tl_intg_err | 1.650s | 157.736us | 5 | 5 | 100.00 | |
| gpio_sec_cm | 1.440s | 98.214us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 5 | 5 | 100.00 | |||
| gpio_tl_intg_err | 1.650s | 157.736us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 6 | 10 | 60.00 | |||
| gpio_rand_straps | 0.930s | 48.559us | 6 | 10 | 60.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 15.020s | 1186.252us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 13 test runs | |||
| gpio_stress_all | 57456302484136205151379238227193734060838165426237378107386363840511233538669 | 347 |
UVM_INFO @ 524105923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 64716096595253862443031714054361548673147544887012726539017202980564982630742 | 75 |
UVM_INFO @ 1268872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 92019473209235323171295733736296227607088974549550830628038087746048675995211 | 75 |
UVM_INFO @ 4511986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 24882713201571744965407085564997090180966127384462917377145964702510706056883 | 77 |
UVM_INFO @ 36162190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 42371450830490408227598007525595709662100399667957796727929387690123894718243 | 191 |
UVM_INFO @ 353123910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 91339532409397605124728040247630776185573042150427530894505719484487992859331 | 75 |
UVM_INFO @ 1255644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 4408101056423456720678405888518978096540550666350809623932784877430102101073 | 369 |
UVM_INFO @ 1710728584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 47411415805461221603112445815460667029935780054511909782584510321451948132911 | 75 |
UVM_INFO @ 7763495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 15091983842377359329132536345062755069298526163036598454398799122240964589990 | 1606 |
UVM_INFO @ 4052291149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 6459371559696374677952313459843477240994038872566447330558466718999574481628 | 1167 |
UVM_INFO @ 20519689560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 50946278645067792944467352518969148951122728797715574543730048591505652150272 | 517 |
UVM_INFO @ 11090454710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 85958242174826020561755852136705190898779595916757251188668182546423878797582 | 76 |
UVM_INFO @ 121567154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 6226576544114435195555174643314841835802725845810989055746068675850445852635 | 75 |
UVM_INFO @ 2537157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) | 7 test runs | |||
| gpio_stress_all_with_rand_reset | 74668970430598671588466141194479067968564518753684067210629767816640980291602 | 236 |
UVM_INFO @ 3744724228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 44533858666982942403834466926551980091420221370566728289434444538509538644707 | 80 |
UVM_INFO @ 10563557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 94819874269599976131881446449323464389807681356166641042952192506970798730060 | 298 |
UVM_INFO @ 3981446159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 86840778881979593018036899717043635364218746562111783749084866288023406148425 | 81 |
UVM_INFO @ 252759631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 37118452855410892630202532596389642709314088582060265669786058184327007196995 | 442 |
UVM_INFO @ 1186251587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 65191099915303326071430907275316485134668442331162125596536897422138971834963 | 85 |
UVM_INFO @ 18881623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 6426741022651188511673740691661004214712993687152231268308907480913741153307 | 81 |
UVM_INFO @ 174018460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 3 test runs | |||
| gpio_stress_all_with_rand_reset | 95532299656850646065106463587456021628814829544081367118979669920664907458071 | 78 |
UVM_INFO @ 25682151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 106176175419292979075369081494603024134357541558194204638794726870171268421953 | 78 |
UVM_INFO @ 7055670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 72370278689466684357699852482172115153750623120217124773791645609213904905499 | 78 |
UVM_INFO @ 301042614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|