Simulation Results: hmac

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.82 %
  • code
  • 99.25 %
  • assert
  • 97.36 %
  • func
  • 99.84 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 14.590s 314.447us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.080s 159.135us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.200s 29.863us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.880s 557.841us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.290s 396.399us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 256.200s 129036.384us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.200s 29.863us 5 5 100.00
hmac_csr_aliasing 5.290s 396.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 57.580s 14714.305us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 96.040s 1683.679us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 255.040s 34071.328us 30 30 100.00
hmac_test_sha384_vectors 611.390s 33353.757us 75 75 100.00
hmac_test_sha512_vectors 548.070s 56250.419us 75 75 100.00
hmac_test_hmac256_vectors 15.790s 378.688us 50 50 100.00
hmac_test_hmac384_vectors 16.260s 1290.888us 60 60 100.00
hmac_test_hmac512_vectors 18.940s 869.871us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 36.470s 24973.719us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1394.580s 27275.911us 10 10 100.00
error 10 10 100.00
hmac_error 105.410s 6195.590us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 118.900s 2558.929us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 14.590s 314.447us 10 10 100.00
hmac_long_msg 57.580s 14714.305us 10 10 100.00
hmac_back_pressure 96.040s 1683.679us 25 25 100.00
hmac_datapath_stress 1394.580s 27275.911us 10 10 100.00
hmac_burst_wr 36.470s 24973.719us 50 50 100.00
hmac_stress_all 5019.250s 304366.831us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 14.590s 314.447us 10 10 100.00
hmac_long_msg 57.580s 14714.305us 10 10 100.00
hmac_back_pressure 96.040s 1683.679us 25 25 100.00
hmac_datapath_stress 1394.580s 27275.911us 10 10 100.00
hmac_wipe_secret 118.900s 2558.929us 10 10 100.00
hmac_test_sha256_vectors 255.040s 34071.328us 30 30 100.00
hmac_test_sha384_vectors 611.390s 33353.757us 75 75 100.00
hmac_test_sha512_vectors 548.070s 56250.419us 75 75 100.00
hmac_test_hmac256_vectors 15.790s 378.688us 50 50 100.00
hmac_test_hmac384_vectors 16.260s 1290.888us 60 60 100.00
hmac_test_hmac512_vectors 18.940s 869.871us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 14.590s 314.447us 10 10 100.00
hmac_long_msg 57.580s 14714.305us 10 10 100.00
hmac_back_pressure 96.040s 1683.679us 25 25 100.00
hmac_datapath_stress 1394.580s 27275.911us 10 10 100.00
hmac_burst_wr 36.470s 24973.719us 50 50 100.00
hmac_error 105.410s 6195.590us 10 10 100.00
hmac_wipe_secret 118.900s 2558.929us 10 10 100.00
hmac_test_sha256_vectors 255.040s 34071.328us 30 30 100.00
hmac_test_sha384_vectors 611.390s 33353.757us 75 75 100.00
hmac_test_sha512_vectors 548.070s 56250.419us 75 75 100.00
hmac_test_hmac256_vectors 15.790s 378.688us 50 50 100.00
hmac_test_hmac384_vectors 16.260s 1290.888us 60 60 100.00
hmac_test_hmac512_vectors 18.940s 869.871us 75 75 100.00
hmac_stress_all 5019.250s 304366.831us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 5019.250s 304366.831us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.940s 59.756us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.930s 15.179us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
hmac_tl_errors 4.120s 163.837us 5 5 100.00
tl_d_illegal_access 5 5 100.00
hmac_tl_errors 4.120s 163.837us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.080s 159.135us 1 1 100.00
hmac_csr_rw 1.200s 29.863us 5 5 100.00
hmac_csr_aliasing 5.290s 396.399us 1 1 100.00
hmac_same_csr_outstanding 2.420s 44.848us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.080s 159.135us 1 1 100.00
hmac_csr_rw 1.200s 29.863us 5 5 100.00
hmac_csr_aliasing 5.290s 396.399us 1 1 100.00
hmac_same_csr_outstanding 2.420s 44.848us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
hmac_sec_cm 1.350s 119.961us 5 5 100.00
hmac_tl_intg_err 3.460s 148.010us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
hmac_tl_intg_err 3.460s 148.010us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 14.590s 314.447us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.400s 579.575us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 669.840s 10348.724us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.890s 174.617us 1 1 100.00