Simulation Results: keymgr

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.95 %
  • code
  • 98.23 %
  • assert
  • 97.72 %
  • func
  • 88.90 %
  • line
  • 99.16 %
  • branch
  • 99.00 %
  • cond
  • 97.24 %
  • toggle
  • 98.06 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
98.73%
V2S
98.82%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
keymgr_smoke 25.870s 3500.363us 10 10 100.00
random 10 10 100.00
keymgr_random 11.200s 1423.828us 10 10 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.370s 23.363us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.750s 49.048us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 15.790s 1286.055us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 7.250s 261.557us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.830s 152.369us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.750s 49.048us 5 5 100.00
keymgr_csr_aliasing 7.250s 261.557us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 10 10 100.00
keymgr_cfg_regwen 83.800s 8945.752us 10 10 100.00
sideload 40 40 100.00
keymgr_sideload 9.660s 476.164us 10 10 100.00
keymgr_sideload_kmac 4.990s 709.278us 10 10 100.00
keymgr_sideload_aes 38.990s 1581.776us 10 10 100.00
keymgr_sideload_otbn 11.420s 1109.161us 10 10 100.00
direct_to_disabled_state 10 10 100.00
keymgr_direct_to_disabled 16.560s 2124.975us 10 10 100.00
lc_disable 9 10 90.00
keymgr_lc_disable 4.630s 932.096us 9 10 90.00
kmac_error_response 9 10 90.00
keymgr_kmac_rsp_err 7.770s 746.356us 9 10 90.00
invalid_sw_input 10 10 100.00
keymgr_sw_invalid_input 53.710s 7809.229us 10 10 100.00
invalid_hw_input 10 10 100.00
keymgr_hwsw_invalid_input 21.660s 1437.718us 10 10 100.00
sync_async_fault_cross 10 10 100.00
keymgr_sync_async_fault_cross 11.030s 2410.607us 10 10 100.00
stress_all 10 10 100.00
keymgr_stress_all 137.000s 8622.827us 10 10 100.00
intr_test 10 10 100.00
keymgr_intr_test 1.130s 14.102us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.260s 133.037us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
keymgr_tl_errors 4.810s 138.860us 5 5 100.00
tl_d_illegal_access 5 5 100.00
keymgr_tl_errors 4.810s 138.860us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.370s 23.363us 1 1 100.00
keymgr_csr_rw 1.750s 49.048us 5 5 100.00
keymgr_csr_aliasing 7.250s 261.557us 1 1 100.00
keymgr_same_csr_outstanding 2.780s 39.988us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.370s 23.363us 1 1 100.00
keymgr_csr_rw 1.750s 49.048us 5 5 100.00
keymgr_csr_aliasing 7.250s 261.557us 1 1 100.00
keymgr_same_csr_outstanding 2.780s 39.988us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
tl_intg_err 10 10 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
keymgr_tl_intg_err 5.130s 390.209us 5 5 100.00
shadow_reg_update_error 5 5 100.00
keymgr_shadow_reg_errors 3.950s 193.319us 5 5 100.00
shadow_reg_read_clear_staged_value 5 5 100.00
keymgr_shadow_reg_errors 3.950s 193.319us 5 5 100.00
shadow_reg_storage_error 5 5 100.00
keymgr_shadow_reg_errors 3.950s 193.319us 5 5 100.00
shadowed_reset_glitch 5 5 100.00
keymgr_shadow_reg_errors 3.950s 193.319us 5 5 100.00
shadow_reg_update_error_with_csr_rw 5 5 100.00
keymgr_shadow_reg_errors_with_csr_rw 15.910s 1011.344us 5 5 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
keymgr_tl_intg_err 5.130s 390.209us 5 5 100.00
sec_cm_config_shadow 5 5 100.00
keymgr_shadow_reg_errors 3.950s 193.319us 5 5 100.00
sec_cm_op_config_regwen 10 10 100.00
keymgr_cfg_regwen 83.800s 8945.752us 10 10 100.00
sec_cm_reseed_config_regwen 15 15 100.00
keymgr_random 11.200s 1423.828us 10 10 100.00
keymgr_csr_rw 1.750s 49.048us 5 5 100.00
sec_cm_sw_binding_config_regwen 15 15 100.00
keymgr_random 11.200s 1423.828us 10 10 100.00
keymgr_csr_rw 1.750s 49.048us 5 5 100.00
sec_cm_max_key_ver_config_regwen 15 15 100.00
keymgr_random 11.200s 1423.828us 10 10 100.00
keymgr_csr_rw 1.750s 49.048us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 9 10 90.00
keymgr_lc_disable 4.630s 932.096us 9 10 90.00
sec_cm_constants_consistency 10 10 100.00
keymgr_hwsw_invalid_input 21.660s 1437.718us 10 10 100.00
sec_cm_intersig_consistency 10 10 100.00
keymgr_hwsw_invalid_input 21.660s 1437.718us 10 10 100.00
sec_cm_hw_key_sw_noaccess 10 10 100.00
keymgr_random 11.200s 1423.828us 10 10 100.00
sec_cm_output_keys_ctrl_redun 10 10 100.00
keymgr_sideload_protect 21.120s 3618.436us 10 10 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_ctrl_fsm_consistency 10 10 100.00
keymgr_custom_cm 5.920s 1600.702us 10 10 100.00
sec_cm_ctrl_fsm_global_esc 9 10 90.00
keymgr_lc_disable 4.630s 932.096us 9 10 90.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 10 10 100.00
keymgr_custom_cm 5.920s 1600.702us 10 10 100.00
sec_cm_kmac_if_done_ctrl_consistency 10 10 100.00
keymgr_custom_cm 5.920s 1600.702us 10 10 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 10 10 100.00
keymgr_custom_cm 5.920s 1600.702us 10 10 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.230s 2559.213us 5 5 100.00
sec_cm_ctrl_key_integrity 10 10 100.00
keymgr_custom_cm 5.920s 1600.702us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
keymgr_stress_all_with_rand_reset 20.500s 6504.426us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
keymgr_stress_all_with_rand_reset 16865834811993517624809971502774648420002399532950709702937097200656252277163 138
UVM_INFO @ 1233402175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 28199602631552218238758701671877836183992221024602262276487708734128659751353 158
UVM_INFO @ 239624245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 82935134329407005363323650661369208172266224549437641697188455342362444345058 137
UVM_INFO @ 504482724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45967390309520301468235319798557544502679072511386895500300565519900300777619 1107
UVM_INFO @ 1538344384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 1 test run
keymgr_lc_disable 19148418097371630801711073641951712742806367463045854609244889435628580724888 295
UVM_INFO @ 269660956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly 1 test run
keymgr_kmac_rsp_err 48902852261130945703301827630545784985005541168269432749386258406918509786794 532
UVM_INFO @ 24429720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---