Simulation Results: kmac/masked

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.55 %
  • code
  • 93.97 %
  • assert
  • 97.98 %
  • func
  • 97.71 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 78.87 %
Validation stages
V1
100.00%
V2
99.70%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 94.020s 37551.873us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.270s 21.098us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.580s 29.433us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.340s 602.653us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 10.140s 1515.912us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 3.520s 419.929us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.580s 29.433us 5 5 100.00
kmac_csr_aliasing 10.140s 1515.912us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.010s 15.248us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.440s 18.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 3491.070s 230965.199us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 1000.980s 24570.185us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2399.500s 356188.199us 5 5 100.00
kmac_test_vectors_sha3_256 2194.660s 541437.585us 5 5 100.00
kmac_test_vectors_sha3_384 1522.910s 134619.843us 5 5 100.00
kmac_test_vectors_sha3_512 1237.540s 47860.765us 5 5 100.00
kmac_test_vectors_shake_128 3153.380s 452763.285us 5 5 100.00
kmac_test_vectors_shake_256 2250.920s 279509.598us 5 5 100.00
kmac_test_vectors_kmac 3.570s 432.019us 5 5 100.00
kmac_test_vectors_kmac_xof 4.860s 1637.384us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 519.990s 115630.570us 20 20 100.00
app 20 20 100.00
kmac_app 370.580s 56114.567us 20 20 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 358.230s 17663.760us 10 10 100.00
entropy_refresh 19 20 95.00
kmac_entropy_refresh 373.320s 73764.367us 19 20 95.00
error 20 20 100.00
kmac_error 399.940s 80767.084us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 14.030s 5645.390us 20 20 100.00
sideload_invalid 20 20 100.00
kmac_sideload_invalid 8.750s 244.784us 20 20 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 41.260s 1500.020us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 36.090s 1652.383us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 69.900s 31228.136us 10 10 100.00
lc_escalation 20 20 100.00
kmac_lc_escalation 16.710s 2034.105us 20 20 100.00
stress_all 20 20 100.00
kmac_stress_all 2363.630s 348337.125us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.200s 16.703us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.220s 18.177us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
kmac_tl_errors 3.860s 110.201us 5 5 100.00
tl_d_illegal_access 5 5 100.00
kmac_tl_errors 3.860s 110.201us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.270s 21.098us 1 1 100.00
kmac_csr_rw 1.580s 29.433us 5 5 100.00
kmac_csr_aliasing 10.140s 1515.912us 1 1 100.00
kmac_same_csr_outstanding 3.040s 149.503us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.270s 21.098us 1 1 100.00
kmac_csr_rw 1.580s 29.433us 5 5 100.00
kmac_csr_aliasing 10.140s 1515.912us 1 1 100.00
kmac_same_csr_outstanding 3.040s 149.503us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 5 5 100.00
kmac_shadow_reg_errors 2.550s 164.906us 5 5 100.00
shadow_reg_read_clear_staged_value 5 5 100.00
kmac_shadow_reg_errors 2.550s 164.906us 5 5 100.00
shadow_reg_storage_error 5 5 100.00
kmac_shadow_reg_errors 2.550s 164.906us 5 5 100.00
shadowed_reset_glitch 5 5 100.00
kmac_shadow_reg_errors 2.550s 164.906us 5 5 100.00
shadow_reg_update_error_with_csr_rw 5 5 100.00
kmac_shadow_reg_errors_with_csr_rw 6.060s 524.285us 5 5 100.00
tl_intg_err 10 10 100.00
kmac_sec_cm 119.600s 34436.141us 5 5 100.00
kmac_tl_intg_err 5.930s 901.318us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
kmac_tl_intg_err 5.930s 901.318us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 20 20 100.00
kmac_lc_escalation 16.710s 2034.105us 20 20 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 94.020s 37551.873us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 519.990s 115630.570us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 5 5 100.00
kmac_shadow_reg_errors 2.550s 164.906us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 119.600s 34436.141us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 119.600s 34436.141us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 119.600s 34436.141us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 94.020s 37551.873us 20 20 100.00
sec_cm_fsm_global_esc 20 20 100.00
kmac_lc_escalation 16.710s 2034.105us 20 20 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 119.600s 34436.141us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 402.170s 27363.234us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 94.020s 37551.873us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
kmac_stress_all_with_rand_reset 207.790s 5941.835us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * 1 test run
kmac_entropy_refresh 41666962033807317009219326342371839263262462606518995564963923328187904313625 221
UVM_INFO @ 20330315754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---