Simulation Results: kmac/unmasked

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.24 %
  • code
  • 92.01 %
  • assert
  • 97.90 %
  • func
  • 95.82 %
  • line
  • 97.56 %
  • branch
  • 95.85 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 71.90 %
Validation stages
V1
100.00%
V2
97.92%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 67.440s 31524.837us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.350s 42.861us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.490s 43.539us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.430s 925.921us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.640s 205.575us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 2.140s 30.079us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.490s 43.539us 5 5 100.00
kmac_csr_aliasing 5.640s 205.575us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.070s 21.813us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.620s 26.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 3344.530s 122841.696us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 936.860s 75906.417us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1967.610s 127864.326us 5 5 100.00
kmac_test_vectors_sha3_256 2266.450s 522375.163us 5 5 100.00
kmac_test_vectors_sha3_384 1272.720s 59260.245us 5 5 100.00
kmac_test_vectors_sha3_512 974.160s 58408.224us 5 5 100.00
kmac_test_vectors_shake_128 2277.600s 143932.823us 5 5 100.00
kmac_test_vectors_shake_256 1784.830s 59122.963us 5 5 100.00
kmac_test_vectors_kmac 2.990s 390.663us 5 5 100.00
kmac_test_vectors_kmac_xof 3.250s 126.196us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 385.290s 20231.318us 20 20 100.00
app 20 20 100.00
kmac_app 290.590s 32693.611us 20 20 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 205.130s 13136.140us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 256.070s 27792.676us 20 20 100.00
error 20 20 100.00
kmac_error 405.900s 34329.489us 20 20 100.00
key_error 19 20 95.00
kmac_key_error 12.760s 8551.297us 19 20 95.00
sideload_invalid 14 20 70.00
kmac_sideload_invalid 58.880s 10018.254us 14 20 70.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 44.100s 1380.957us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 36.340s 2235.319us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 58.690s 22123.622us 10 10 100.00
lc_escalation 20 20 100.00
kmac_lc_escalation 37.540s 2716.942us 20 20 100.00
stress_all 20 20 100.00
kmac_stress_all 1709.780s 323745.132us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.150s 175.162us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.160s 28.672us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
kmac_tl_errors 3.640s 1047.638us 5 5 100.00
tl_d_illegal_access 5 5 100.00
kmac_tl_errors 3.640s 1047.638us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.350s 42.861us 1 1 100.00
kmac_csr_rw 1.490s 43.539us 5 5 100.00
kmac_csr_aliasing 5.640s 205.575us 1 1 100.00
kmac_same_csr_outstanding 2.910s 108.565us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.350s 42.861us 1 1 100.00
kmac_csr_rw 1.490s 43.539us 5 5 100.00
kmac_csr_aliasing 5.640s 205.575us 1 1 100.00
kmac_same_csr_outstanding 2.910s 108.565us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 5 5 100.00
kmac_shadow_reg_errors 2.610s 135.206us 5 5 100.00
shadow_reg_read_clear_staged_value 5 5 100.00
kmac_shadow_reg_errors 2.610s 135.206us 5 5 100.00
shadow_reg_storage_error 5 5 100.00
kmac_shadow_reg_errors 2.610s 135.206us 5 5 100.00
shadowed_reset_glitch 5 5 100.00
kmac_shadow_reg_errors 2.610s 135.206us 5 5 100.00
shadow_reg_update_error_with_csr_rw 5 5 100.00
kmac_shadow_reg_errors_with_csr_rw 4.610s 78.179us 5 5 100.00
tl_intg_err 10 10 100.00
kmac_sec_cm 80.260s 5497.842us 5 5 100.00
kmac_tl_intg_err 4.060s 399.095us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
kmac_tl_intg_err 4.060s 399.095us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 20 20 100.00
kmac_lc_escalation 37.540s 2716.942us 20 20 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 67.440s 31524.837us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 385.290s 20231.318us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 5 5 100.00
kmac_shadow_reg_errors 2.610s 135.206us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 80.260s 5497.842us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 80.260s 5497.842us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 80.260s 5497.842us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 67.440s 31524.837us 20 20 100.00
sec_cm_fsm_global_esc 20 20 100.00
kmac_lc_escalation 37.540s 2716.942us 20 20 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 80.260s 5497.842us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 249.740s 61999.120us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 67.440s 31524.837us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
kmac_stress_all_with_rand_reset 380.320s 58216.141us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
kmac_stress_all_with_rand_reset 66109808503273201316704803387564179503666384180389100955092070720230613454620 154
UVM_INFO @ 1982894317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 93130195657924542261008185369949443082950127461073697428267154452172520673949 275
UVM_INFO @ 18168643765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 56232999267797600185312856344278301960326780305942375146621963072836168027828 212
UVM_INFO @ 7625756690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 61867757598245647896640737118709333930434195422467731580395328230071517118209 151
UVM_INFO @ 2099367449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 64281613975910292696828493181758629015330348179910626361650325993372654724641 245
UVM_INFO @ 5393453979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 3 test runs
kmac_sideload_invalid 103032659655397611532387749866731354150230638755543795561665388623741413106327 78
UVM_INFO @ 10018254263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 14225104767924000977797933665406661299382485421900325174504568989969748279725 78
UVM_INFO @ 10032522740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 52892897047983966167797710876167040045884263193473609874204406936066768849944 78
UVM_INFO @ 10039527959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) 1 test run
kmac_sideload_invalid 97543376973961100117215406366615949795293916573046736518007534551136643271589 86
UVM_INFO @ 10252683011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 1 test run
kmac_sideload_invalid 63918953741171086319595451280613966233604893714401252730969933220730646484670 79
UVM_INFO @ 10092767851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * 1 test run
kmac_key_error 55372695670783855676288114739660879607938490629698795635881271980984877811506 77
UVM_INFO @ 124968616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
kmac_sideload_invalid 26972679773334808101238567718694999658715860056140584642090429337595718456416 82
UVM_INFO @ 10179748068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---