Simulation Results: lc_ctrl/volatile_unlock_disabled

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.98 %
  • code
  • 85.73 %
  • assert
  • 94.13 %
  • func
  • 96.09 %
  • line
  • 97.26 %
  • branch
  • 94.12 %
  • cond
  • 80.44 %
  • toggle
  • 89.54 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
99.72%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
lc_ctrl_smoke 5.170s 98.494us 10 10 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.320s 21.507us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.330s 15.313us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.620s 85.510us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.200s 36.146us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.340s 27.420us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.330s 15.313us 5 5 100.00
lc_ctrl_csr_aliasing 2.200s 36.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 10 10 100.00
lc_ctrl_state_post_trans 10.930s 94.665us 10 10 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.630s 1183.675us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.350s 13.713us 10 10 100.00
lc_prog_failure 10 10 100.00
lc_ctrl_prog_failure 3.340s 70.201us 10 10 100.00
lc_state_failure 10 10 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_errors 10 10 100.00
lc_ctrl_errors 16.320s 793.534us 10 10 100.00
security_escalation 99 100 99.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_prog_failure 3.340s 70.201us 10 10 100.00
lc_ctrl_errors 16.320s 793.534us 10 10 100.00
lc_ctrl_security_escalation 8.790s 324.485us 10 10 100.00
lc_ctrl_jtag_state_failure 78.280s 14936.934us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.750s 1841.212us 20 20 100.00
lc_ctrl_jtag_errors 68.070s 11631.576us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 14.810s 734.785us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.790s 1787.206us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.750s 1841.212us 20 20 100.00
lc_ctrl_jtag_errors 68.070s 11631.576us 19 20 95.00
lc_ctrl_jtag_access 15.440s 681.861us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 30.200s 3207.425us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.310s 178.661us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.980s 597.737us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 21.390s 1058.294us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.930s 1619.027us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.510s 50.902us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.060s 144.223us 10 10 100.00
lc_ctrl_jtag_alert_test 2.070s 229.755us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 20.980s 5816.484us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.340s 14.982us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 649.140s 25839.667us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.530s 34.013us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
lc_ctrl_tl_errors 2.650s 84.159us 5 5 100.00
tl_d_illegal_access 5 5 100.00
lc_ctrl_tl_errors 2.650s 84.159us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.320s 21.507us 1 1 100.00
lc_ctrl_csr_rw 1.330s 15.313us 5 5 100.00
lc_ctrl_csr_aliasing 2.200s 36.146us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.920s 108.022us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.320s 21.507us 1 1 100.00
lc_ctrl_csr_rw 1.330s 15.313us 5 5 100.00
lc_ctrl_csr_aliasing 2.200s 36.146us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.920s 108.022us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
lc_ctrl_tl_intg_err 3.670s 110.265us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
lc_ctrl_tl_intg_err 3.670s 110.265us 5 5 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.630s 1183.675us 10 10 100.00
sec_cm_manuf_state_sparse 15 15 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
sec_cm_transition_ctr_sparse 15 15 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 15 15 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 15 15 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
sec_cm_state_config_sparse 15 15 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
sec_cm_main_fsm_sparse 15 15 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
sec_cm_kmac_fsm_sparse 15 15 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
sec_cm_main_fsm_local_esc 15 15 100.00
lc_ctrl_state_failure 14.580s 339.888us 10 10 100.00
lc_ctrl_sec_cm 9.980s 685.333us 5 5 100.00
sec_cm_main_fsm_global_esc 10 10 100.00
lc_ctrl_security_escalation 8.790s 324.485us 10 10 100.00
sec_cm_main_ctrl_flow_consistency 30 30 100.00
lc_ctrl_state_post_trans 10.930s 94.665us 10 10 100.00
lc_ctrl_jtag_state_post_trans 15.790s 1787.206us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.850s 819.562us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.850s 819.562us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 13.770s 1085.609us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 13.880s 2943.455us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 13.880s 2943.455us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 63.560s 5910.214us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 69354454118253440384113000426224300238706527546584969299288633402810802634758 921
UVM_INFO @ 343892257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 111258306293965895546762326506678586875049199663400478124269867002249942945932 3569
UVM_INFO @ 76110817581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18554520261403453205905224705095960240018792412569240579094469107762866453699 166
UVM_INFO @ 3389358481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 72140398881394839177185873830451261641815218736825559791084439759839242874580 150
UVM_INFO @ 205273835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67463187807515555340326921654195225370331890521063447086237174859703615065232 6206
UVM_INFO @ 4516452727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 81091457727481985468931541081556636552774103060802008901533600073212403151181 2522
UVM_INFO @ 4765092452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---