Simulation Results: lc_ctrl/volatile_unlock_enabled

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.12 %
  • code
  • 85.96 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.24 %
  • branch
  • 94.21 %
  • cond
  • 80.59 %
  • toggle
  • 89.54 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.44%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
lc_ctrl_smoke 4.220s 86.109us 10 10 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.490s 131.344us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.200s 44.158us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.750s 120.347us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 81.474us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.880s 91.154us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.200s 44.158us 5 5 100.00
lc_ctrl_csr_aliasing 1.460s 81.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 10 10 100.00
lc_ctrl_state_post_trans 6.950s 64.397us 10 10 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.870s 358.220us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.250s 43.359us 10 10 100.00
lc_prog_failure 10 10 100.00
lc_ctrl_prog_failure 3.300s 148.542us 10 10 100.00
lc_state_failure 10 10 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_errors 9 10 90.00
lc_ctrl_errors 8.540s 320.441us 9 10 90.00
security_escalation 98 100 98.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_prog_failure 3.300s 148.542us 10 10 100.00
lc_ctrl_errors 8.540s 320.441us 9 10 90.00
lc_ctrl_security_escalation 9.090s 2495.640us 10 10 100.00
lc_ctrl_jtag_state_failure 76.450s 3911.824us 20 20 100.00
lc_ctrl_jtag_prog_failure 10.370s 875.923us 20 20 100.00
lc_ctrl_jtag_errors 65.580s 11949.018us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 13.860s 770.567us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.990s 651.691us 20 20 100.00
lc_ctrl_jtag_prog_failure 10.370s 875.923us 20 20 100.00
lc_ctrl_jtag_errors 65.580s 11949.018us 19 20 95.00
lc_ctrl_jtag_access 21.950s 1239.035us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 27.110s 4147.640us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.700s 381.278us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.830s 163.804us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 36.210s 8984.609us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 22.060s 2020.423us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.020s 33.725us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.600s 965.681us 10 10 100.00
lc_ctrl_jtag_alert_test 3.030s 350.903us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 11.890s 2278.385us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.410s 59.537us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 305.900s 45055.801us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.680s 32.088us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
lc_ctrl_tl_errors 4.340s 134.156us 5 5 100.00
tl_d_illegal_access 5 5 100.00
lc_ctrl_tl_errors 4.340s 134.156us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.490s 131.344us 1 1 100.00
lc_ctrl_csr_rw 1.200s 44.158us 5 5 100.00
lc_ctrl_csr_aliasing 1.460s 81.474us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.240s 90.776us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.490s 131.344us 1 1 100.00
lc_ctrl_csr_rw 1.200s 44.158us 5 5 100.00
lc_ctrl_csr_aliasing 1.460s 81.474us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.240s 90.776us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
lc_ctrl_tl_intg_err 2.200s 453.335us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
lc_ctrl_tl_intg_err 2.200s 453.335us 5 5 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.870s 358.220us 10 10 100.00
sec_cm_manuf_state_sparse 15 15 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
sec_cm_transition_ctr_sparse 15 15 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 15 15 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 15 15 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
sec_cm_state_config_sparse 15 15 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
sec_cm_main_fsm_sparse 15 15 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
sec_cm_kmac_fsm_sparse 15 15 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
sec_cm_main_fsm_local_esc 15 15 100.00
lc_ctrl_state_failure 13.650s 425.006us 10 10 100.00
lc_ctrl_sec_cm 9.150s 1979.696us 5 5 100.00
sec_cm_main_fsm_global_esc 10 10 100.00
lc_ctrl_security_escalation 9.090s 2495.640us 10 10 100.00
sec_cm_main_ctrl_flow_consistency 30 30 100.00
lc_ctrl_state_post_trans 6.950s 64.397us 10 10 100.00
lc_ctrl_jtag_state_post_trans 18.990s 651.691us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.350s 1568.771us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.350s 1568.771us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.550s 654.027us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.160s 1364.087us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.160s 1364.087us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 118.740s 4506.108us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 41211099418530361353538588381295707715309471102286797073116050223487865541911 385
UVM_INFO @ 1133977770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23737691156473165149641708216030755109355366878642465529128836832978000671021 9542
UVM_INFO @ 14069505916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20978559121399528646510835022983111958151087017192976125662673391416234815940 2280
UVM_INFO @ 3148321457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23919049149627464106836303400032624362579771299129148332198338533499323045078 5528
UVM_INFO @ 47759558206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54387840551019254182333899244803766005035613596173905842649978272760639188758 758
UVM_INFO @ 2418556425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_errors 46026771882620547382089205502053927444420841784144108498459472297459718289819 1440
UVM_INFO @ 163958318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 62741280389866732267702047077573756333818084045662405019869236608456383791502 2083
UVM_INFO @ 3309294642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error 1 test run
lc_ctrl_stress_all_with_rand_reset 71944214564106111029450778331024885428496614387772804872651475492950700823691 2473
UVM_INFO @ 2544406264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---