Simulation Results: otbn

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.76 %
  • code
  • 96.66 %
  • assert
  • 90.62 %
  • func
  • 100.00 %
  • block
  • 99.47 %
  • line
  • 99.64 %
  • branch
  • 93.25 %
  • toggle
  • 93.74 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.80%
V2S
96.12%
V3
20.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 39.000s 44.675us 1 1 100.00
single_binary 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 35.000s 35.421us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 35.000s 14.634us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 36.000s 40.774us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 36.000s 21.341us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 36.000s 122.555us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 35.000s 14.634us 5 5 100.00
otbn_csr_aliasing 36.000s 21.341us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 92.000s 1740.280us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 82.000s 4030.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 52.000s 510.615us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 71.000s 2293.695us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 109.000s 1236.500us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 174.000s 393.192us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 74.000s 299.278us 59 60 98.33
zero_state_err_urnd 0 5 0.00
otbn_zero_state_err_urnd 28.000s 9.608us 0 5 0.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 32.000s 22.873us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 36.000s 19.707us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 35.000s 26.378us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
otbn_tl_errors 30.000s 270.687us 5 5 100.00
tl_d_illegal_access 5 5 100.00
otbn_tl_errors 30.000s 270.687us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 35.000s 35.421us 1 1 100.00
otbn_csr_rw 35.000s 14.634us 5 5 100.00
otbn_csr_aliasing 36.000s 21.341us 1 1 100.00
otbn_same_csr_outstanding 34.000s 42.480us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 35.000s 35.421us 1 1 100.00
otbn_csr_rw 35.000s 14.634us 5 5 100.00
otbn_csr_aliasing 36.000s 21.341us 1 1 100.00
otbn_same_csr_outstanding 34.000s 42.480us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 38.000s 51.374us 10 10 100.00
otbn_dmem_err 38.000s 136.920us 15 15 100.00
internal_integrity 15 17 88.24
otbn_alu_bignum_mod_err 39.000s 60.207us 5 5 100.00
otbn_controller_ispr_rdata_err 38.000s 25.166us 5 5 100.00
otbn_mac_bignum_acc_err 36.000s 55.155us 5 5 100.00
otbn_urnd_err 34.000s 45.071us 0 2 0.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 35.000s 27.661us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 35.000s 12.732us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 35.000s 15.342us 8 10 80.00
tl_intg_err 10 10 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
otbn_tl_intg_err 76.000s 453.082us 5 5 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 55.000s 595.521us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 39.000s 44.675us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 38.000s 136.920us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 38.000s 51.374us 10 10 100.00
sec_cm_bus_integrity 5 5 100.00
otbn_tl_intg_err 76.000s 453.082us 5 5 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 74.000s 299.278us 59 60 98.33
sec_cm_controller_fsm_local_esc 35 40 87.50
otbn_imem_err 38.000s 51.374us 10 10 100.00
otbn_dmem_err 38.000s 136.920us 15 15 100.00
otbn_zero_state_err_urnd 28.000s 9.608us 0 5 0.00
otbn_illegal_mem_acc 35.000s 27.661us 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 35 40 87.50
otbn_imem_err 38.000s 51.374us 10 10 100.00
otbn_dmem_err 38.000s 136.920us 15 15 100.00
otbn_zero_state_err_urnd 28.000s 9.608us 0 5 0.00
otbn_illegal_mem_acc 35.000s 27.661us 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 74.000s 299.278us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 35 40 87.50
otbn_imem_err 38.000s 51.374us 10 10 100.00
otbn_dmem_err 38.000s 136.920us 15 15 100.00
otbn_zero_state_err_urnd 28.000s 9.608us 0 5 0.00
otbn_illegal_mem_acc 35.000s 27.661us 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 35.000s 21.220us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 37.000s 14.089us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 58.000s 75.318us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 58.000s 75.318us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 36.000s 16.395us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 41.000s 65.476us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 34.000s 58.143us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 34.000s 58.143us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 33.000s 14.000us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 109.000s 1236.500us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 36.000s 37.773us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 36.000s 84.639us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 246.000s 1140.272us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 538.000s 1620.290us 2 10 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 33.000s 166.186us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 5 test runs
otbn_zero_state_err_urnd 48080013582059202971931224396928508615892280072518440486356579446925310242448 110
UVM_INFO @ 9607694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 15284175664186292871213331147673444928152351926206334461218818735856587655201 115
UVM_INFO @ 1434912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 42837237445011575896102009139106085004399382295773959596798676574491886824323 112
UVM_INFO @ 34253999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 98891413477946948147918164181493822635649337069033382983945978318456101788271 108
UVM_INFO @ 7239829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 84166957330073486829306666092432460114329319967705347841011453198199200213106 112
UVM_INFO @ 20858257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
otbn_stress_all_with_rand_reset 101103413374653337095911662924135015034641698085048859680556747188003370524856 353
UVM_INFO @ 485782817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 71841618520293869585936629144294091994097900044776553320427492457515593702352 154
UVM_INFO @ 125069045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 68720183987044109325998422190280928521497847287997934824450792883454383092617 418
UVM_INFO @ 2261220767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 97777563492159986353173683138204950724985973974196594229213092752121033960455 475
UVM_INFO @ 1012278110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 62739015251656373417769702515290226158812451786888227768162415783712374337732 510
UVM_INFO @ 1295966442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 2 test runs
otbn_urnd_err 91324577987935101066207759486166950926901450936572684285254701684688680492346 110
UVM_INFO @ 45070730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_urnd_err 94691241629769258009412785807358545127879322090679869782706622987959517501190 106
UVM_INFO @ 3176913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_stack_addr_integ_chk 21543732940174603535661932908515220645178254157335335800259903446013666622099 114
UVM_ERROR @ 30270499 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 30270499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 113056255779524924122064330659751067736971194776463085874490527537982655381499 116
UVM_ERROR @ 12929507 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 12929507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [otbn_dmem_err_vseq] expect alert:fatal to fire 1 test run
otbn_stress_all_with_rand_reset 12940657179561627395941570404876462179096289143587498308872880680356289082643 203
UVM_INFO @ 406662332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 5201189063044529053592176378914992076137469740826333290293417707231023775992 381
UVM_INFO @ 2721057590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 86289355491949493402140552300379195150764743984586562663783258584365623327131 86
UVM_INFO @ 1432373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_partial_wipe 77697917903140661086969201657736916177050726788770348729392663905375637551409 116
UVM_INFO @ 16678980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed 1 test run
otbn_partial_wipe 38255039448386356197167385868479083431200880765344018909159948768644250302599 114
UVM_ERROR @ 15948163 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 15948163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 30295497085251925349543439345510102663546901980208708322025939363682911445578 158
UVM_INFO @ 21153144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---