Simulation Results: otp_ctrl

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.73 %
  • code
  • 85.93 %
  • assert
  • 94.75 %
  • func
  • 91.50 %
  • line
  • 90.35 %
  • branch
  • 86.56 %
  • cond
  • 93.91 %
  • toggle
  • 95.96 %
  • FSM
  • 62.85 %
Validation stages
V1
96.15%
V2
93.42%
V2S
92.68%
V3
20.79%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.150s 196.270us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 8.170s 320.972us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.150s 982.647us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.200s 580.973us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.400s 1931.151us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.280s 391.022us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.420s 1570.445us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.200s 580.973us 5 5 100.00
otp_ctrl_csr_aliasing 3.280s 391.022us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.070s 512.860us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.310s 37.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.640s 1576.835us 1 1 100.00
init_fail 276 300 92.00
otp_ctrl_init_fail 6.630s 1790.081us 276 300 92.00
partition_check 11 20 55.00
otp_ctrl_background_chks 20.310s 1426.588us 8 10 80.00
otp_ctrl_check_fail 14.030s 2043.251us 3 10 30.00
regwen_during_otp_init 10 10 100.00
otp_ctrl_regwen 9.440s 4137.695us 10 10 100.00
partition_lock 10 10 100.00
otp_ctrl_dai_lock 27.900s 4803.277us 10 10 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 29.940s 1877.652us 10 10 100.00
lc_interactions 209 210 99.52
otp_ctrl_parallel_lc_req 14.690s 1143.111us 10 10 100.00
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
otp_dai_errors 10 10 100.00
otp_ctrl_dai_errs 32.100s 6226.643us 10 10 100.00
otp_macro_errors 4 10 40.00
otp_ctrl_macro_errs 18.140s 2338.471us 4 10 40.00
test_access 10 10 100.00
otp_ctrl_test_access 27.510s 3223.471us 10 10 100.00
stress_all 8 10 80.00
otp_ctrl_stress_all 370.970s 218657.819us 8 10 80.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.370s 493.669us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.200s 988.646us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
otp_ctrl_tl_errors 4.040s 289.823us 5 5 100.00
tl_d_illegal_access 5 5 100.00
otp_ctrl_tl_errors 4.040s 289.823us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.150s 982.647us 1 1 100.00
otp_ctrl_csr_rw 2.200s 580.973us 5 5 100.00
otp_ctrl_csr_aliasing 3.280s 391.022us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.770s 1744.281us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.150s 982.647us 1 1 100.00
otp_ctrl_csr_rw 2.200s 580.973us 5 5 100.00
otp_ctrl_csr_aliasing 3.280s 391.022us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.770s 1744.281us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
tl_intg_err 7 10 70.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
otp_ctrl_tl_intg_err 17.760s 5035.177us 5 5 100.00
prim_count_check 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
prim_fsm_check 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_bus_integrity 5 5 100.00
otp_ctrl_tl_intg_err 17.760s 5035.177us 5 5 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 8.170s 320.972us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 8.170s 320.972us 10 10 100.00
sec_cm_dai_fsm_sparse 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_kdi_fsm_sparse 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_lci_fsm_sparse 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_part_fsm_sparse 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_scrmbl_fsm_sparse 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_timer_fsm_sparse 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_dai_ctr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_kdi_seed_ctr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_kdi_entropy_ctr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_lci_ctr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_part_ctr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_scrmbl_ctr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_timer_integ_ctr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_timer_cnsty_ctr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_timer_lfsr_redun 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_dai_fsm_local_esc 201 205 98.05
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_lci_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
sec_cm_kdi_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
sec_cm_part_fsm_local_esc 203 210 96.67
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
otp_ctrl_macro_errs 18.140s 2338.471us 4 10 40.00
sec_cm_scrmbl_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
sec_cm_timer_fsm_local_esc 201 205 98.05
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_dai_fsm_global_esc 201 205 98.05
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_lci_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
sec_cm_kdi_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
sec_cm_part_fsm_global_esc 203 210 96.67
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
otp_ctrl_macro_errs 18.140s 2338.471us 4 10 40.00
sec_cm_scrmbl_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
sec_cm_timer_fsm_global_esc 201 205 98.05
otp_ctrl_parallel_lc_esc 35.100s 13339.965us 199 200 99.50
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_part_data_reg_integrity 276 300 92.00
otp_ctrl_init_fail 6.630s 1790.081us 276 300 92.00
sec_cm_part_data_reg_bkgn_chk 3 10 30.00
otp_ctrl_check_fail 14.030s 2043.251us 3 10 30.00
sec_cm_part_mem_regren 10 10 100.00
otp_ctrl_dai_lock 27.900s 4803.277us 10 10 100.00
sec_cm_part_mem_sw_unreadable 10 10 100.00
otp_ctrl_dai_lock 27.900s 4803.277us 10 10 100.00
sec_cm_part_mem_sw_unwritable 10 10 100.00
otp_ctrl_dai_lock 27.900s 4803.277us 10 10 100.00
sec_cm_lc_part_mem_sw_noaccess 10 10 100.00
otp_ctrl_dai_lock 27.900s 4803.277us 10 10 100.00
sec_cm_access_ctrl_mubi 10 10 100.00
otp_ctrl_dai_lock 27.900s 4803.277us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 8.170s 320.972us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
otp_ctrl_dai_lock 27.900s 4803.277us 10 10 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 8.170s 320.972us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 2 5 40.00
otp_ctrl_sec_cm 450.780s 170760.567us 2 5 40.00
sec_cm_direct_access_config_regwen 10 10 100.00
otp_ctrl_regwen 9.440s 4137.695us 10 10 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 8.170s 320.972us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 8.170s 320.972us 10 10 100.00
sec_cm_macro_mem_integrity 4 10 40.00
otp_ctrl_macro_errs 18.140s 2338.471us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.990s 3433.884us 1 1 100.00
stress_all_with_rand_reset 20 100 20.00
otp_ctrl_stress_all_with_rand_reset 182.620s 72423.873us 20 100 20.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 30 test runs
otp_ctrl_stress_all_with_rand_reset 50985540038190566693371370651705561046538112479211014613474754139519012124905 11414
UVM_INFO @ 2338293713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87143243761218914226305160601057489324400873109308459417392365656276848424887 1432
UVM_INFO @ 73521653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54487852997774058172755228176875365711054462089558558881786668825774932290045 2695
UVM_INFO @ 15283878894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50639892651888849376296964742912390897743311513453504552601725980321318827370 23814
UVM_INFO @ 4039130708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6938317456019949847587602581519660547911532954489556402435403683152009864218 19146
UVM_INFO @ 9529125961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101347657352346471408972941638755878160842760999149973117284808088008848103698 9573
UVM_INFO @ 2042073061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114584953868005037376800535282734450358400286354237883111977279745609119276814 31099
UVM_INFO @ 7594942306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61757116503495789135997877434644232785545623975914496609987205602707304754078 11845
UVM_INFO @ 773801306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55964779097367304944378084905090098906242533850585099131574387142582513006606 20709
UVM_INFO @ 3785168777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61745798475593159119042631480174662950079941521901262554002304492065932120163 7244
UVM_INFO @ 1054693673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104558582293336200326986245355844514214562206913403041525773662628539203435085 92
UVM_INFO @ 29266782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71631875370002882614319034914931062482110747423545487112107537587962751651627 39437
UVM_INFO @ 1565491281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43332169943536963294096255652130416721981270827462962595835477803214992460621 1676
UVM_INFO @ 2761234367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94010558784688102004103801259323109411580682353244473528595427373987217352200 27714
UVM_INFO @ 2914200470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86955163386958945834038398360241323090399980946369495375079372019950008404928 37488
UVM_INFO @ 72423873451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48360803195172340255178492731263830742950784500937408266542850560463585802302 92
UVM_INFO @ 58642934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 93273356464540140673405452051259096821184548915678846589120716891497173889426 188
UVM_INFO @ 2995236292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24386764007049731155628725271770484544469281295083646269251995943946570614938 93
UVM_INFO @ 58758416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18670956319925153160144619993304616654113896078878818986488566346572979274440 3470
UVM_INFO @ 6543350810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59112410753845447510183881287915962395862784796492358505390684795272367756707 232
UVM_INFO @ 128952858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10167970932051193700949749673439907789618611677074362812100559305950876679038 92
UVM_INFO @ 53856164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99401184303962509330642062773964293710443431905016222433626477561045735084674 138
UVM_INFO @ 2155459380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61321599466986788234523832608035706940160078171075724941803533335014121217 308
UVM_INFO @ 237612562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72545017839502324264151866239618706617095400877323187482521960532860376874562 92
UVM_INFO @ 27875118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55688491914486236741675839975377689614308771623090960312211832328224196426821 276
UVM_INFO @ 1054381750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12833911449122864453241018851315924243843533812684489576793135391327855001693 572
UVM_INFO @ 241427504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105405754330349598799601214734027181480918782558344895456307575276738241043645 3284
UVM_INFO @ 397777676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103161216657877075299798213276473356282151398344286134539126726934249799957679 92
UVM_INFO @ 425910540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109085086756419340642903078611415812910428010593266346268323790006325778066352 32141
UVM_INFO @ 29234899607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105756403611269657818480932112388721637807906231311269562324023956545005985898 15815
UVM_INFO @ 14530480801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 24 test runs
otp_ctrl_stress_all 88598628582292318971156849710489441209990795790853183183038569057759964310172 51527
UVM_INFO @ 1582207899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 17716706132743649979968361530439159084772303630763183344617456787718046690231 4776
UVM_INFO @ 323472957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 115148018860285099633863718150168956215475178685534699181724682354486962410131 4642
UVM_INFO @ 422436381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73595516053904770580232152767357928874513707571873681251684171230727678605426 543
UVM_INFO @ 498076407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 80698165848182730570525065506800538443110379260147627310054161078502175346160 7293
UVM_INFO @ 993605489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44354106725021698201652687324613349417484682673197923263614527579410197335494 1287
UVM_INFO @ 1176726074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 71680465020542486714212672167738790185172170510624533932715872860834879450157 451
UVM_INFO @ 119327230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 113116677278518110813885553374322267613760478501283815870227642930061592076160 9855
UVM_INFO @ 2338471178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 43342718574770124219367370197799932906817194057555465588141999713360383292888 1741
UVM_INFO @ 243868315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 2258914468468743505710048683249806065407354046614383266386610684323702223706 8339
UVM_INFO @ 2591648866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 44073243102435704936007595359814792189951391194423890305487674669222947999512 611
UVM_INFO @ 46289906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 12587449048532767746691385297213534491829705350892115406141970746764419061759 601
UVM_INFO @ 59416099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39749850450098209410135217113001958137855372435717120328729944246341526430778 4783
UVM_INFO @ 12598086769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16855070598152164606359564056531048573441908779586947030410408060709775394631 3052
UVM_INFO @ 274334179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75648760047419096055287657866912049436877845436930970554859512905401956316152 10540
UVM_INFO @ 6885808012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58524246891115234869692823652935584414878915917939290336769398473877904343129 941
UVM_INFO @ 2031879041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66874684706826733517849590062391763157332870215877766284657968990886991193621 16305
UVM_INFO @ 23997900134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65602967443227345512740999195667057442464123376894668622249703272115084011605 3956
UVM_INFO @ 495046160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83545349947236231495037936094648171880142495833952771399404508051146386342068 1752
UVM_INFO @ 1014855528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53732393736565009232002886719350378221378188363956319333700321324116446242257 10080
UVM_INFO @ 15613871909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41953209788667219475625748622839626525003316238665130943318191525874691725130 2776
UVM_INFO @ 1921086952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50399321327973012001317393433801209397924461187268964933274719829175209528252 14564
UVM_INFO @ 2016679439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76282660740005704433464150469566277507091310212976762810803777456303444754750 11704
UVM_INFO @ 31391774485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60309692864978413440036143486888434394363714418644227747367081273716634817040 7476
UVM_INFO @ 3604795068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 21 test runs
otp_ctrl_init_fail 95885688838729327127684696127209606884061554906171910420680145291998698815534 2841
UVM_INFO @ 196997637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 95923072385144305419758025709225245750156246198616386593023955720217981727367 1863
UVM_INFO @ 313756846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 9105745584315205046466404525433157576637692205025575665050681831335558212086 1491
UVM_INFO @ 501152825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 70985673888877972054784227148094784207977914176297885436442132857027145885147 2019
UVM_INFO @ 278275228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 15357739682569199797975286461411642295278436711757428326003972724468772118733 2555
UVM_INFO @ 382820394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 21196071627240932311104096737103623480109008042161099789599356308348329823272 2193
UVM_INFO @ 159899825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 98405071512429408262673749357187676778012716233198690177283058907706100808710 1425
UVM_INFO @ 1790080932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 66596203873107693091702468452205505460551561897455246955011651035822090839995 2809
UVM_INFO @ 300016225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 112450768154208019362916217906628221941358809262015866187783858584423325137936 3305
UVM_INFO @ 1542074484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 5681510621655614344912375806384644773547602494497345308258186588989245207681 1573
UVM_INFO @ 1464090921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 58455611617099096004684905664665948375983383057932866260026955862608659749357 1755
UVM_INFO @ 1339177270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 40120113147609791539108093548714250664027166732477016120092785298661508898341 1831
UVM_INFO @ 1581181451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 17908498673502748833529258076144644572607723556722715929374382260247355374852 1253
UVM_INFO @ 472184417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 23644497690560469630549435628683998597087739324213165688681046991914264760866 1333
UVM_INFO @ 211977087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 107651402992440457970824106854410141344316349900637109188034716394740307824035 2313
UVM_INFO @ 973694876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 53383017625168895104266987553414777374487969531252433524510049233652314468278 3581
UVM_INFO @ 1234624417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 93168528125574387481127928309272779423035305079052253603353075255430713151624 2785
UVM_INFO @ 1239984051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 83442665277271955884722904785161994798410537628619859693983700007775781299969 2557
UVM_INFO @ 93471070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 57955471171540415137682761203946194619332768419132168916259573445683797759065 2455
UVM_INFO @ 255345937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 61647304337460382137751652190072733902304889928129809998532694741334911067799 1885
UVM_INFO @ 198478443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 14007099513459443107849595061674240687901617684709121376591353752290128965079 843
UVM_INFO @ 1965368033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 19 test runs
otp_ctrl_stress_all_with_rand_reset 46587432689088749797703339312247613073221849978043139276797128432241771787664 33194
UVM_INFO @ 18433358268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98372436658210233017807170354434190654398625046339843008940404720186664425579 21331
UVM_INFO @ 45719415448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 21856843743237935427627325578583155633117183410800987810430705425596422437997 12874
UVM_INFO @ 2043250519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63284827286714124428925298062628351620552703363586219235229220940663642486633 6504
UVM_INFO @ 15715556061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51778044182507657697847364681745020455994028942764624547018721520465450880410 8981
UVM_INFO @ 5426976420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27481097139253891741388009795992011434400670557475797872019447000929121822631 4875
UVM_INFO @ 527928665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101865186600020254867803687782542527514775659627126842393338811161904496496717 4399
UVM_INFO @ 1104488452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85396603441235126421104493995787339725022975723955664409423055676541379404049 3034
UVM_INFO @ 17163385018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99239417779074097755762984239812424034295974720398880314623878032664515318868 3788
UVM_INFO @ 5759293074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48060882104386335613564829756702282406655205311572077617645324233650511090822 24872
UVM_INFO @ 9491243050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13005981231643238239502699192267991511590141423609366942657090775593400200130 5245
UVM_INFO @ 800032834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76129039870449447315725386503780328509473048169443612994913580037422720409009 8912
UVM_INFO @ 8986421260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18402891833308612452692470711011682798302465642770214264313524231788760047086 20689
UVM_INFO @ 1325827426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35062455241260593506294859696568807405345446963170820504771974822932497368148 4711
UVM_INFO @ 1880687496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54133258598125476739240130998533948927442740619753070012893696921281314823944 6642
UVM_INFO @ 13583680381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12062419447655050828369826030993641756374236132724858563870089077178377700864 2045
UVM_INFO @ 3440459120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103143501816434886968290761571686916073980784433179366829406390807921023781753 3458
UVM_INFO @ 3429051346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35268097542338549669445063189984737113696189804038174853710984034814543837229 4104
UVM_INFO @ 5862364652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7528531252095694603242191462469292337687417877740523683807919606702554876430 11225
UVM_INFO @ 1619837926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 13 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 51296807692540902756301820005694026794364548113644564505286931442695325793184 92
UVM_INFO @ 46288559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68422528398679082021777677577931927636817824153239872872719869256274335095783 92
UVM_INFO @ 54455958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32658804187183212058068188243935022569329737295406479618756492748733919174787 1582
UVM_INFO @ 255073294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91105881010096461207220032970594266758387899103259269637058074894304559802450 1599
UVM_INFO @ 1690359226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22718226603564136217034823398544284354928145066291788830887984278782067935522 1388
UVM_INFO @ 791857346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113228756174515001156274939162013421326201603751342039153955065955200309015012 136
UVM_INFO @ 314110949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45356230429294996210303926413187842316786451499528543773626426232945100881651 139
UVM_INFO @ 4320237532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82985194713983714380584641405192882421264816276914370949706349892031311057391 92
UVM_INFO @ 39021450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75068649091143771642509792007810083008005455958432466906322143621162774919979 12856
UVM_INFO @ 1208229537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78123582863939977309762615639291938634558089522002357675523592952123648547493 1691
UVM_INFO @ 3782386396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18703202102567093197515985206692919557810956097115616785382528188911101347736 1624
UVM_INFO @ 2649570113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36860930637732040621869457729809042042099696123521424925078750373950255527240 231
UVM_INFO @ 8512323260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 93199060623172024998523948516168462148871043073788955690197582064607589099643 244
UVM_INFO @ 72248789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 5 test runs
otp_ctrl_background_chks 53376378224738051539541450757973062850722901960667299172647898427336939722547 9893
UVM_INFO @ 2787568591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 21582740838886750823181944251857444659404100203583658301586802222170554697892 12951
UVM_INFO @ 17241421004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 51204185881391145611026809358997381362575284044942791545114283875215181986351 175175
UVM_INFO @ 12304646082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63950905640863797082527841471989366720520410201060277642894703474708195445983 5272
UVM_INFO @ 8037837854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26323205716417412711888169525472529751544590218580150633718862207473735046350 3884
UVM_INFO @ 459588982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q 3 test runs
otp_ctrl_check_fail 59227502892574833532663833331076156694537109322396336152677301685263736603297 1981
UVM_INFO @ 69619361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 47990687134633409233186602290634203408253694430880999266272607184816956949833 2463
UVM_INFO @ 144712267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 53096058643186214527582568697647479979973915514869861482439217196065774500230 2647
UVM_INFO @ 225099385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire 3 test runs
otp_ctrl_sec_cm 74588957800390113224704523583747984704235239328814898027324599341861455518517 1072
UVM_INFO @ 66846725369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_sec_cm 41325013060334685224116605795288465455795952798702706732209958155559457191643 1550
UVM_INFO @ 89192380193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_sec_cm 82507105169459594213312382967937419191962258977463341484069193728945179420050 1447
UVM_INFO @ 91667718028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 2 test runs
otp_ctrl_stress_all_with_rand_reset 28489951208783198870082024222889379933618968692594686530404308469645394878807 1237
UVM_INFO @ 7922607808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101167434100292671075727866288702160292078659140243643831368266916718333068958 85733
UVM_INFO @ 15006766873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:* 2 test runs
otp_ctrl_macro_errs 61730351574806129728483817084633327675388186161280507655848906719322256818331 2905
UVM_INFO @ 4744553625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 87080282060668216607925074213248877937664822671585482042062075958235775468937 9944
UVM_INFO @ 685148012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 56286226702611617620154792360290118334590400371852793729825774364237103784337 7428
UVM_INFO @ 16160629777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 13135803505880027722899634787456430435282045646487054459412066681612896618387 10723
UVM_INFO @ 11481294108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* 1 test run
otp_ctrl_parallel_lc_esc 83049379353203564886810422778938886144868213812352022378643712838836573859237 3527
UVM_INFO @ 76781275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_macro_error does not trigger! 1 test run
otp_ctrl_init_fail 112274145810113029268317996237482025597113040375821227774043671874265704295672 1457
UVM_INFO @ 1810730907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---