Simulation Results: pwrmgr

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 94.66 %
  • assert
  • 96.34 %
  • func
  • 97.86 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.77 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
89.74%
V2S
88.24%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 1.020s 25.462us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 1.000s 37.534us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 1.040s 18.534us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 3.140s 135.180us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.500s 49.316us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.490s 67.257us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 1.040s 18.534us 5 5 100.00
pwrmgr_csr_aliasing 1.500s 49.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.380s 129.859us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.380s 129.859us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.290s 80.349us 10 10 100.00
pwrmgr_lowpower_invalid 1.080s 76.829us 10 10 100.00
reset 14 20 70.00
pwrmgr_reset 4.450s 1000.000us 7 10 70.00
pwrmgr_reset_invalid 1.350s 99.017us 7 10 70.00
main_power_glitch_reset 7 10 70.00
pwrmgr_reset 4.450s 1000.000us 7 10 70.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.560s 927.291us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.580s 209.448us 10 10 100.00
disable_rom_integrity_check 9 10 90.00
pwrmgr_disable_rom_integrity_check 2.200s 1000.000us 9 10 90.00
stress_all 5 10 50.00
pwrmgr_stress_all 34.900s 10198.549us 5 10 50.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.970s 66.640us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
pwrmgr_tl_errors 1.850s 162.698us 5 5 100.00
tl_d_illegal_access 5 5 100.00
pwrmgr_tl_errors 1.850s 162.698us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 1.000s 37.534us 1 1 100.00
pwrmgr_csr_rw 1.040s 18.534us 5 5 100.00
pwrmgr_csr_aliasing 1.500s 49.316us 1 1 100.00
pwrmgr_same_csr_outstanding 1.280s 35.835us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 1.000s 37.534us 1 1 100.00
pwrmgr_csr_rw 1.040s 18.534us 5 5 100.00
pwrmgr_csr_aliasing 1.500s 49.316us 1 1 100.00
pwrmgr_same_csr_outstanding 1.280s 35.835us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 10 0.00
pwrmgr_tl_intg_err 0.980s 8.534us 0 5 0.00
pwrmgr_sec_cm 1.160s 33.781us 0 5 0.00
prim_count_check 0 5 0.00
pwrmgr_sec_cm 1.160s 33.781us 0 5 0.00
prim_fsm_check 0 5 0.00
pwrmgr_sec_cm 1.160s 33.781us 0 5 0.00
sec_cm_bus_integrity 0 5 0.00
pwrmgr_tl_intg_err 0.980s 8.534us 0 5 0.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.490s 675.881us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 10 10 100.00
pwrmgr_wakeup_reset 1.560s 927.291us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.300s 52.600us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.930s 32.189us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 0 5 0.00
pwrmgr_sec_cm 1.160s 33.781us 0 5 0.00
sec_cm_fsm_sparse 0 5 0.00
pwrmgr_sec_cm 1.160s 33.781us 0 5 0.00
sec_cm_fsm_terminal 0 5 0.00
pwrmgr_sec_cm 1.160s 33.781us 0 5 0.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.990s 73.800us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.970s 80.694us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.760s 217.980us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 1.040s 18.534us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 1.040s 18.534us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 6 10 60.00
pwrmgr_escalation_timeout 1.280s 677.803us 6 10 60.00
stress_all_with_rand_reset 8 10 80.00
pwrmgr_stress_all_with_rand_reset 24.990s 14941.211us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire 10 test runs
pwrmgr_tl_intg_err 52829678690234430966742634510942412725898235481228241326086279035261453163437 78
UVM_INFO @ 7648242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 95268350641471085994931541389633022770731263243185585933546985957549407742847 85
UVM_INFO @ 33781480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 11935318118185351485929288878740988936398925181375078888660175366879288696287 85
UVM_INFO @ 10188864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 22414638224166977179491185019663871317031016983064167879225800672176964316578 82
UVM_INFO @ 15164898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 115313788241818660331107036719495122476168351700825440017907982092711147479630 82
UVM_INFO @ 8358319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 17959628819482995635209527803651744490225088476842579873262810495805404972935 77
UVM_INFO @ 7327759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 69882155728755996655442016543391938141819681318098572072158729697163989033302 85
UVM_INFO @ 7851218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 26687419797520849544260001858251256881811604720343189755931467863955115346417 78
UVM_INFO @ 7324733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 45985716084303370280638385557308602321417317506832589914447444109875570605494 82
UVM_INFO @ 8533703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 57869041324244052747151714644244054800517640530885485942586138495117238166425 85
UVM_INFO @ 39484516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 6 test runs
pwrmgr_stress_all 39546126732724575294386425966649622122528401313187889287750614715268085717860 176
UVM_INFO @ 10145438542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 17009076574797928797018231145324044113362456997856788801531771764919539883483 222
UVM_INFO @ 10198549308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 105089975939041885413918319054976344922371580957458631385045457911201093527597 757
UVM_INFO @ 11983194509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 66881465465882901169962954247308379765389317652591675933409007531742479517327 298
UVM_INFO @ 10623779915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all_with_rand_reset 23789216167192128856478348109083444410116331935645456241541133450845780114037 618
UVM_INFO @ 14496687825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 92450118160416704543447973737397377276546662394174690724573602944036494340393 1022
UVM_INFO @ 11486795792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
pwrmgr_reset 69694496774021666876421695358462783182648729549702514395520927326765885242354 195
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 52000409800519025469930086563225786930370035464349939214141035866825175785478 112
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 38934996339844183423181830351612572890619243198284831646110898866462017236685 169
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 25554225246197319627045347843392543635537199374773200266095524685144390432460 116
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 4 test runs
pwrmgr_escalation_timeout 108209841857869724290479692308476106762978995623697004696462686508531113883804 79
UVM_ERROR @ 99184963 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 99184963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 354677998729150864518364720240408179900340556024192656965113842029194496218 79
UVM_ERROR @ 677803307 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 677803307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 64223135216558508115720605982200747508180545906795483446913640671701647503661 79
UVM_ERROR @ 300050837 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 300050837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 74906502787241274387617331090400568556230150342353427436303982024127894600486 79
UVM_ERROR @ 216333332 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 216333332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit 1 test run
pwrmgr_reset_invalid 103920348745255027706496962694993537504875706303188815660613245192688600073474 160
UVM_INFO @ 73384465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
pwrmgr_stress_all_with_rand_reset 49515160842521685349995550913662290162414844488355486580370648056513354925938 1231
UVM_INFO @ 1915977187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLcInit 1 test run
pwrmgr_reset_invalid 104358442808653870868071518161451578756099011470066811892725090626410718505086 133
UVM_INFO @ 98718449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower 1 test run
pwrmgr_reset_invalid 7359097241332389454403183848983541740121094888367832347424943047711824790514 96
UVM_INFO @ 46575200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---