Simulation Results: rom_ctrl/32kb

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.43 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 98.81 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.31%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.160s 176.074us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.210s 540.631us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 6.770s 170.362us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.090s 289.056us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.370s 544.475us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.530s 217.499us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 6.770s 170.362us 5 5 100.00
rom_ctrl_csr_aliasing 5.370s 544.475us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.540s 170.317us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.220s 173.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 4.370s 400.795us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 40.880s 2085.155us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 11.100s 1042.158us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 6.900s 167.223us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
rom_ctrl_tl_errors 14.100s 554.680us 5 5 100.00
tl_d_illegal_access 5 5 100.00
rom_ctrl_tl_errors 14.100s 554.680us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.210s 540.631us 1 1 100.00
rom_ctrl_csr_rw 6.770s 170.362us 5 5 100.00
rom_ctrl_csr_aliasing 5.370s 544.475us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.320s 2634.598us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.210s 540.631us 1 1 100.00
rom_ctrl_csr_rw 6.770s 170.362us 5 5 100.00
rom_ctrl_csr_aliasing 5.370s 544.475us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.320s 2634.598us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.480s 2279.352us 5 5 100.00
tl_intg_err 10 10 100.00
rom_ctrl_sec_cm 297.400s 3410.519us 5 5 100.00
rom_ctrl_tl_intg_err 51.690s 304.761us 5 5 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 297.400s 3410.519us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 297.400s 3410.519us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 297.400s 3410.519us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 297.400s 3410.519us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.160s 176.074us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.160s 176.074us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.160s 176.074us 2 2 100.00
sec_cm_bus_integrity 5 5 100.00
rom_ctrl_tl_intg_err 51.690s 304.761us 5 5 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
rom_ctrl_kmac_err_chk 11.100s 1042.158us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 124.890s 36018.518us 17 20 85.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.480s 2279.352us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 297.400s 3410.519us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 486.130s 5268.384us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 76439161413359045821035634280214857237855893368875683639910763216011078161051 100
UVM_INFO @ 1368412415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 90671073285909135479012422092631758061778188042293468648931688323781360489666 101
UVM_INFO @ 8163187036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 76039342386229133578568635120212839843387293997026191059140260830944259917551 97
UVM_INFO @ 3699796033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---