Simulation Results: rom_ctrl/64kb

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.19 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 98.09 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 9.060s 773.240us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 16.850s 798.613us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 10.460s 555.698us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 11.560s 1068.223us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.750s 2393.045us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 13.220s 308.956us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 10.460s 555.698us 5 5 100.00
rom_ctrl_csr_aliasing 8.750s 2393.045us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.950s 373.253us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 10.700s 290.129us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 12.880s 5849.539us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 53.330s 4229.557us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 26.510s 1465.744us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 10.750s 1026.993us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
rom_ctrl_tl_errors 18.110s 4955.077us 5 5 100.00
tl_d_illegal_access 5 5 100.00
rom_ctrl_tl_errors 18.110s 4955.077us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 16.850s 798.613us 1 1 100.00
rom_ctrl_csr_rw 10.460s 555.698us 5 5 100.00
rom_ctrl_csr_aliasing 8.750s 2393.045us 1 1 100.00
rom_ctrl_same_csr_outstanding 12.900s 462.496us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 16.850s 798.613us 1 1 100.00
rom_ctrl_csr_rw 10.460s 555.698us 5 5 100.00
rom_ctrl_csr_aliasing 8.750s 2393.045us 1 1 100.00
rom_ctrl_same_csr_outstanding 12.900s 462.496us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 73.820s 6091.666us 5 5 100.00
tl_intg_err 10 10 100.00
rom_ctrl_sec_cm 623.100s 1560.883us 5 5 100.00
rom_ctrl_tl_intg_err 124.710s 698.827us 5 5 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 623.100s 1560.883us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 623.100s 1560.883us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 623.100s 1560.883us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 623.100s 1560.883us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 9.060s 773.240us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 9.060s 773.240us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 9.060s 773.240us 2 2 100.00
sec_cm_bus_integrity 5 5 100.00
rom_ctrl_tl_intg_err 124.710s 698.827us 5 5 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
rom_ctrl_kmac_err_chk 26.510s 1465.744us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 299.870s 48342.446us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 73.820s 6091.666us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 623.100s 1560.883us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 409.280s 4785.215us 20 20 100.00