Simulation Results: rstmgr

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.83 %
  • code
  • 99.59 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.17 %
  • toggle
  • 99.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 2.100s 256.490us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.410s 142.946us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.170s 71.655us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.260s 280.915us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.730s 106.361us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.670s 148.158us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.170s 71.655us 5 5 100.00
rstmgr_csr_aliasing 1.730s 106.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 1.440s 214.910us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 2.690s 444.692us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.740s 198.745us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 7.100s 1701.037us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 7.100s 1701.037us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 7.100s 1701.037us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 7.100s 1701.037us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 59.470s 12320.680us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.220s 97.815us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
rstmgr_tl_errors 3.610s 612.662us 5 5 100.00
tl_d_illegal_access 5 5 100.00
rstmgr_tl_errors 3.610s 612.662us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.410s 142.946us 1 1 100.00
rstmgr_csr_rw 1.170s 71.655us 5 5 100.00
rstmgr_csr_aliasing 1.730s 106.361us 1 1 100.00
rstmgr_same_csr_outstanding 1.730s 97.623us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.410s 142.946us 1 1 100.00
rstmgr_csr_rw 1.170s 71.655us 5 5 100.00
rstmgr_csr_aliasing 1.730s 106.361us 1 1 100.00
rstmgr_same_csr_outstanding 1.730s 97.623us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
rstmgr_sec_cm 45.470s 16800.997us 5 5 100.00
rstmgr_tl_intg_err 2.970s 502.711us 5 5 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 45.470s 16800.997us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 45.470s 16800.997us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
rstmgr_tl_intg_err 2.970s 502.711us 5 5 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.490s 169.362us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 5 5 100.00
rstmgr_leaf_rst_cnsty 11.770s 2446.512us 5 5 100.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 1.820s 302.114us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 45.470s 16800.997us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.170s 71.655us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.170s 71.655us 5 5 100.00