Simulation Results: rv_timer

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.55 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 98.82 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
83.18%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.340s 615.469us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.920s 34.602us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 0.900s 14.435us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.790s 1461.747us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.200s 221.052us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.350s 203.315us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 0.900s 14.435us 5 5 100.00
rv_timer_csr_aliasing 1.200s 221.052us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 1.590s 1851.771us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 3.520s 2788.830us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 629.990s 1591153.848us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 629.990s 1591153.848us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 8.180s 7343.799us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 0.880s 13.856us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 0.870s 33.000us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
rv_timer_tl_errors 2.680s 854.041us 5 5 100.00
tl_d_illegal_access 5 5 100.00
rv_timer_tl_errors 2.680s 854.041us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 0.920s 34.602us 1 1 100.00
rv_timer_csr_rw 0.900s 14.435us 5 5 100.00
rv_timer_csr_aliasing 1.200s 221.052us 1 1 100.00
rv_timer_same_csr_outstanding 1.080s 95.961us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 0.920s 34.602us 1 1 100.00
rv_timer_csr_rw 0.900s 14.435us 5 5 100.00
rv_timer_csr_aliasing 1.200s 221.052us 1 1 100.00
rv_timer_same_csr_outstanding 1.080s 95.961us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
rv_timer_sec_cm 1.290s 133.323us 5 5 100.00
rv_timer_tl_intg_err 1.750s 1450.400us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
rv_timer_tl_intg_err 1.750s 1450.400us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 1.290s 458.891us 2 10 20.00
max_value 0 10 0.00
rv_timer_max 1.590s 41.907us 0 10 0.00
stress_all_with_rand_reset 18 20 90.00
rv_timer_stress_all_with_rand_reset 60.010s 25282.686us 18 20 90.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 26 test runs
rv_timer_min 8699639564872188465795148366569542855064478265123190264516931298697307757455 77
UVM_INFO @ 794872819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 35882401535180986129148472724700956888886382895984073242694254658237332757889 75
UVM_INFO @ 537486175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 73094055912802833459282731163064552721636286754258988383542856758295502057954 77
UVM_INFO @ 458890841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 87572996595525433243232785814149454885376024894049303567292461631862280465381 75
UVM_INFO @ 285922544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 77918920276490879812375900534077234599474425636471793799872656285164930546936 76
UVM_INFO @ 115555300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 105249342578171936581643320856899701728150859012118269249345458380460887218728 75
UVM_INFO @ 108796874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 100221141357735206690374508972498421936919635517152230460106286799794558444884 75
UVM_INFO @ 122919792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 23388648325591923183357780616120524861654496309252189198208314597446725067932 76
UVM_INFO @ 225211113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 41104192146559217498081777703986100405061664638379739860857083815257502663502 75
UVM_INFO @ 71600530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 46403699690385365803240222820848863850406955987481801896250355753826829400228 75
UVM_INFO @ 1851770511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 113532454055999257933158783857383357771268948363756658299627078939504092939740 76
UVM_INFO @ 217425855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 37056091414105473818844332462462805844270940894751463618284103872993786624808 75
UVM_INFO @ 2504308757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 14048005371927443021059731419506363483995440953326565511876423966766448719575 78
UVM_INFO @ 209792540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 36343018989748270217856208578651002293821561004739483517022989601387458508239 75
UVM_INFO @ 119455175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 46618306439803018388701421937811963825179053331216634859864275241493172750385 75
UVM_INFO @ 61861549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 7430698826662108234563441943260269529459245570332818634879966372009247076353 75
UVM_INFO @ 74380468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 19380469814206439557500056091969166940236825770257274500687599007542775367080 76
UVM_INFO @ 184045595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 47533381978992296442550438845957413822547100059350914561204468314054448033361 76
UVM_INFO @ 74595626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 37958612760664264208783643188971616315802429075615965157915468442826849126478 75
UVM_INFO @ 264285212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 61743995674062552883098970030502962153102155554594766275513571846916052127285 76
UVM_INFO @ 90576762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 2858096788161478840457608306420304098163319850598487807209256770654167589179 76
UVM_INFO @ 150403487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 105568549223405880457192076414116444603075106840414851229898826571142013959606 75
UVM_INFO @ 154689542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 94999427903556844261322155429849130488356823914364575108870596852615555187172 76
UVM_INFO @ 151536028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 63650178048155428319335499448509421466646847316982717229918274924465234108340 75
UVM_INFO @ 242053695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 107267363148127425281165998633829859425064735794949104059914429900768113120172 75
UVM_INFO @ 411756927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 94090983574868192349147909362279257783840302007747749741943072051947547990268 75
UVM_INFO @ 113054546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 58097000855465705378730674427374237367005927748857214499732757774165513911265 75
UVM_INFO @ 91845894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 49222504685286039848401696101280672566638705929572051781760252968881069376129 75
UVM_INFO @ 42346509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 111077406386304303765933775339297088636575181368074816500028712502649653788172 76
UVM_INFO @ 89544936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 69265009124451645619413046162197890196466447880656485474481907389209118076584 75
UVM_INFO @ 175253689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 37685479074983452687989795032678661617443866589582802455614106669162893124718 76
UVM_INFO @ 46014368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 62529098465360293974550416846723057892744809822873092588085741591134628584875 75
UVM_INFO @ 191405670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 13833763967907835121899363164326002491071164311480558857064683584924569388890 75
UVM_INFO @ 83886593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 88361590030182744459540107336005342476302276270392350209983488998917667633708 76
UVM_INFO @ 89215658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 36921568730311893505484643215736941336147090292979943940164935361126391992173 76
UVM_INFO @ 45579631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) 2 test runs
rv_timer_stress_all_with_rand_reset 50893189271556054003390945446803250973678513907129808512139667943335083914250 160
UVM_INFO @ 7842407970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 21287891721130598704371685828441186134056515561334407485371189734587081373557 163
UVM_INFO @ 319897445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 94124868028118774987873678286158866204569596427114961068519531636499293265337 76
UVM_INFO @ 41906608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---