Simulation Results: spi_device/2p

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.28 %
  • code
  • 94.28 %
  • assert
  • 94.74 %
  • func
  • 96.83 %
  • line
  • 99.16 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_device_flash_and_tpm 383.760s 46873.137us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.370s 26.888us 1 1 100.00
csr_rw 5 5 100.00
spi_device_csr_rw 2.810s 1215.967us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 11.190s 8708.658us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 16.260s 609.865us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_device_csr_mem_rw_with_rand_reset 4.810s 238.150us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_device_csr_rw 2.810s 1215.967us 5 5 100.00
spi_device_csr_aliasing 16.260s 609.865us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.050s 13.234us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.770s 76.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 10 10 100.00
spi_device_csb_read 1.170s 90.330us 10 10 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.500s 106.406us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.970s 17.924us 1 1 100.00
tpm_read 10 10 100.00
spi_device_tpm_rw 3.360s 223.668us 10 10 100.00
tpm_write 10 10 100.00
spi_device_tpm_rw 3.360s 223.668us 10 10 100.00
tpm_hw_reg 20 20 100.00
spi_device_tpm_read_hw_reg 12.350s 11823.176us 10 10 100.00
spi_device_tpm_sts_read 1.280s 161.655us 10 10 100.00
tpm_fully_random_case 10 10 100.00
spi_device_tpm_all 31.570s 5331.299us 10 10 100.00
pass_cmd_filtering 20 20 100.00
spi_device_pass_cmd_filtering 23.260s 14101.685us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
pass_addr_translation 20 20 100.00
spi_device_pass_addr_payload_swap 14.000s 5457.006us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
pass_payload_translation 20 20 100.00
spi_device_pass_addr_payload_swap 14.000s 5457.006us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
cmd_info_slots 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
cmd_read_status 20 20 100.00
spi_device_intercept 21.750s 3869.065us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
cmd_read_jedec 20 20 100.00
spi_device_intercept 21.750s 3869.065us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
cmd_read_sfdp 20 20 100.00
spi_device_intercept 21.750s 3869.065us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
cmd_fast_read 20 20 100.00
spi_device_intercept 21.750s 3869.065us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
cmd_read_pipeline 20 20 100.00
spi_device_intercept 21.750s 3869.065us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
flash_cmd_upload 10 10 100.00
spi_device_upload 31.220s 13757.645us 10 10 100.00
mailbox_command 10 10 100.00
spi_device_mailbox 41.040s 23894.657us 10 10 100.00
mailbox_cross_outside_command 10 10 100.00
spi_device_mailbox 41.040s 23894.657us 10 10 100.00
mailbox_cross_inside_command 10 10 100.00
spi_device_mailbox 41.040s 23894.657us 10 10 100.00
cmd_read_buffer 20 20 100.00
spi_device_flash_mode 26.950s 1813.823us 10 10 100.00
spi_device_read_buffer_direct 13.830s 3227.778us 10 10 100.00
cmd_dummy_cycle 20 20 100.00
spi_device_mailbox 41.040s 23894.657us 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
quad_spi 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
dual_spi 10 10 100.00
spi_device_flash_all 198.050s 136360.525us 10 10 100.00
4b_3b_feature 10 10 100.00
spi_device_cfg_cmd 11.580s 1079.709us 10 10 100.00
write_enable_disable 10 10 100.00
spi_device_cfg_cmd 11.580s 1079.709us 10 10 100.00
TPM_with_flash_or_passthrough_mode 10 10 100.00
spi_device_flash_and_tpm 383.760s 46873.137us 10 10 100.00
tpm_and_flash_trans_with_min_inactive_time 10 10 100.00
spi_device_flash_and_tpm_min_idle 184.270s 171107.052us 10 10 100.00
stress_all 10 10 100.00
spi_device_stress_all 444.320s 49845.882us 10 10 100.00
alert_test 10 10 100.00
spi_device_alert_test 1.110s 15.647us 10 10 100.00
intr_test 10 10 100.00
spi_device_intr_test 1.140s 29.476us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
spi_device_tl_errors 5.880s 205.170us 5 5 100.00
tl_d_illegal_access 5 5 100.00
spi_device_tl_errors 5.880s 205.170us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
spi_device_csr_hw_reset 1.370s 26.888us 1 1 100.00
spi_device_csr_rw 2.810s 1215.967us 5 5 100.00
spi_device_csr_aliasing 16.260s 609.865us 1 1 100.00
spi_device_same_csr_outstanding 4.990s 334.881us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_device_csr_hw_reset 1.370s 26.888us 1 1 100.00
spi_device_csr_rw 2.810s 1215.967us 5 5 100.00
spi_device_csr_aliasing 16.260s 609.865us 1 1 100.00
spi_device_same_csr_outstanding 4.990s 334.881us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
spi_device_sec_cm 1.530s 450.749us 5 5 100.00
spi_device_tl_intg_err 20.280s 1634.359us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
spi_device_tl_intg_err 20.280s 1634.359us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_device_flash_mode_ignore_cmds 260.050s 252033.381us 10 10 100.00