Simulation Results: spi_host

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.67 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 90.34 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.36%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 96.000s 9398.054us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 20.687us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 27.162us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 811.819us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 98.593us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 67.879us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 27.162us 5 5 100.00
spi_host_csr_aliasing 1.000s 98.593us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 42.890us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 51.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 23.413us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 5.000s 203.263us 10 10 100.00
spi_host_error_cmd 2.000s 20.079us 10 10 100.00
spi_host_event 211.000s 69343.919us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 919.417us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 919.417us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 919.417us 10 10 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 25.000s 767.318us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 132.805us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 919.417us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 919.417us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 96.000s 9398.054us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 96.000s 9398.054us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 100.000s 11716.176us 10 10 100.00
spien 10 10 100.00
spi_host_spien 216.000s 164462.673us 10 10 100.00
stall 9 10 90.00
spi_host_status_stall 93.000s 15558.733us 9 10 90.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 4.000s 427.759us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 5.000s 203.263us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 47.276us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 105.032us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
spi_host_tl_errors 4.000s 160.066us 5 5 100.00
tl_d_illegal_access 5 5 100.00
spi_host_tl_errors 4.000s 160.066us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 20.687us 1 1 100.00
spi_host_csr_rw 2.000s 27.162us 5 5 100.00
spi_host_csr_aliasing 1.000s 98.593us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 24.701us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 20.687us 1 1 100.00
spi_host_csr_rw 2.000s 27.162us 5 5 100.00
spi_host_csr_aliasing 1.000s 98.593us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 24.701us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 10 100.00
spi_host_tl_intg_err 3.000s 319.360us 5 5 100.00
spi_host_sec_cm 2.000s 237.696us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
spi_host_tl_intg_err 3.000s 319.360us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 5 5 100.00
spi_host_upper_range_clkdiv 449.000s 26299.877us 5 5 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed 1 test run
spi_host_status_stall 87469757774561279330259915377389412423460947128379498828238393457368546962302 796
UVM_ERROR @ 6642371297 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=6642371000 ps
UVM_INFO @ 6642371297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---