Simulation Results: sram_ctrl/main

 
08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.52 %
  • code
  • 96.90 %
  • assert
  • 96.46 %
  • func
  • 96.20 %
  • block
  • 96.28 %
  • line
  • 97.03 %
  • branch
  • 94.49 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 8.000s 7404.255us 5 5 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 37.533us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 1.000s 28.033us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 247.299us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 74.611us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 372.968us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 1.000s 28.033us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 74.611us 1 1 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 297.000s 229926.903us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 162.000s 34961.972us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 42.000s 6193.078us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 261.000s 10383.584us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 198.000s 18997.186us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 97.000s 225415.199us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 56.000s 50908.775us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 49.000s 14261.569us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 8.000s 11024.476us 5 5 100.00
sram_ctrl_partial_access_b2b 348.000s 47600.404us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 9.000s 2658.482us 5 5 100.00
sram_ctrl_throughput_w_partial_write 8.000s 3176.910us 5 5 100.00
sram_ctrl_throughput_w_readback 8.000s 732.319us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 15.000s 5217.900us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 5.000s 722.677us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 607.000s 45392.094us 5 5 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 27.135us 10 10 100.00
tl_d_oob_addr_access 5 5 100.00
sram_ctrl_tl_errors 5.000s 38.872us 5 5 100.00
tl_d_illegal_access 5 5 100.00
sram_ctrl_tl_errors 5.000s 38.872us 5 5 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 37.533us 1 1 100.00
sram_ctrl_csr_rw 1.000s 28.033us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 74.611us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 56.728us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 37.533us 1 1 100.00
sram_ctrl_csr_rw 1.000s 28.033us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 74.611us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 56.728us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 40.000s 14664.375us 5 5 100.00
tl_intg_err 10 10 100.00
sram_ctrl_sec_cm 6.000s 3886.040us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 177.187us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 3886.040us 5 5 100.00
sec_cm_bus_integrity 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 177.187us 5 5 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 15.000s 5217.900us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 15.000s 5217.900us 5 5 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 1.000s 28.033us 5 5 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 49.000s 14261.569us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 49.000s 14261.569us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 49.000s 14261.569us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 56.000s 50908.775us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 8.000s 2773.399us 5 5 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 40.000s 14664.375us 5 5 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 9.000s 2773.018us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 8.000s 7404.255us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 8.000s 7404.255us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 49.000s 14261.569us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 3886.040us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 56.000s 50908.775us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 3886.040us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 3886.040us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 8.000s 7404.255us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 3886.040us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 74.000s 1346.307us 5 5 100.00