| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 75.125us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 23.514us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 48.783us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 3.000s | 1147.495us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 12.231us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 2.000s | 353.746us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 48.783us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 12.231us | 1 | 1 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| sram_ctrl_mem_walk | 11.000s | 466.856us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| sram_ctrl_mem_partial_access | 7.000s | 698.534us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 5 | 5 | 100.00 | |||
| sram_ctrl_multiple_keys | 19.000s | 929.239us | 5 | 5 | 100.00 | |
| stress_pipeline | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_pipeline | 235.000s | 3847.426us | 5 | 5 | 100.00 | |
| bijection | 5 | 5 | 100.00 | |||
| sram_ctrl_bijection | 9.000s | 402.147us | 5 | 5 | 100.00 | |
| access_during_key_req | 5 | 5 | 100.00 | |||
| sram_ctrl_access_during_key_req | 23.000s | 1370.850us | 5 | 5 | 100.00 | |
| lc_escalation | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 1383.708us | 5 | 5 | 100.00 | |
| executable | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 10.000s | 2048.613us | 5 | 5 | 100.00 | |
| partial_access | 10 | 10 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 75.252us | 5 | 5 | 100.00 | |
| sram_ctrl_partial_access_b2b | 368.000s | 77524.757us | 5 | 5 | 100.00 | |
| max_throughput | 15 | 15 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 37.390us | 5 | 5 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 69.225us | 5 | 5 | 100.00 | |
| sram_ctrl_throughput_w_readback | 3.000s | 72.034us | 5 | 5 | 100.00 | |
| regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 1833.436us | 5 | 5 | 100.00 | |
| ram_cfg | 5 | 5 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 27.806us | 5 | 5 | 100.00 | |
| stress_all | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_all | 54.000s | 15266.537us | 5 | 5 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 13.981us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 5 | 5 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 35.717us | 5 | 5 | 100.00 | |
| tl_d_illegal_access | 5 | 5 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 35.717us | 5 | 5 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 23.514us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 48.783us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 12.231us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 28.653us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 23.514us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 48.783us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 12.231us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 28.653us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 518.184us | 5 | 5 | 100.00 | |
| tl_intg_err | 10 | 10 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 756.914us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 1697.677us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 756.914us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 1697.677us | 5 | 5 | 100.00 | |
| sec_cm_ctrl_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 1833.436us | 5 | 5 | 100.00 | |
| sec_cm_readback_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 1833.436us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 48.783us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 10.000s | 2048.613us | 5 | 5 | 100.00 | |
| sec_cm_exec_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 10.000s | 2048.613us | 5 | 5 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 10.000s | 2048.613us | 5 | 5 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 1383.708us | 5 | 5 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 2.000s | 41.491us | 5 | 5 | 100.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 518.184us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 5 | 5 | 100.00 | |||
| sram_ctrl_readback_err | 2.000s | 126.721us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 75.125us | 5 | 5 | 100.00 | |
| sec_cm_addr_scramble | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 75.125us | 5 | 5 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 10.000s | 2048.613us | 5 | 5 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 756.914us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 1383.708us | 5 | 5 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 756.914us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 756.914us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 75.125us | 5 | 5 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 6.000s | 756.914us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 95.000s | 1716.121us | 5 | 5 | 100.00 | |