Simulation Results

Simulation Results: adc_ctrl

15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
67.21 %

code
96.24 %

assert
91.73 %

func
13.66 %

line
98.96 %

branch
97.59 %

cond
87.59 %

toggle
99.76 %

FSM
97.30 %

Validation stages

V1		100.00%
V2		49.72%
V2S		100.00%
V3		20.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	18.180s	5809.697us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	2.010s	1187.840us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	2.360s	509.201us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	24.760s	16715.506us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	2.040s	1516.043us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.260s	452.541us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	2.360s	509.201us	5	5	100.00
	adc_ctrl_csr_aliasing	2.040s	1516.043us	1	1	100.00

88/177 passed

49.72 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.280s	463.265us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.170s	399.514us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	1.910s	405.768us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	1.750s	322.079us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	1.830s	329.064us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.110s	513.512us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	2.330s	459.470us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	1.950s	341.453us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	13.630s	5356.353us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	71.440s	35744.467us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	198.950s	99491.925us	10	10	100.00
stress_all				1	10	10.00
	adc_ctrl_stress_all	62.610s	43189.015us	1	10	10.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.230s	525.306us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.510s	520.092us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	4.170s	541.580us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	4.170s	541.580us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	2.010s	1187.840us	1	1	100.00
	adc_ctrl_csr_rw	2.360s	509.201us	5	5	100.00
	adc_ctrl_csr_aliasing	2.040s	1516.043us	1	1	100.00
	adc_ctrl_same_csr_outstanding	12.460s	4693.679us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	2.010s	1187.840us	1	1	100.00
	adc_ctrl_csr_rw	2.360s	509.201us	5	5	100.00
	adc_ctrl_csr_aliasing	2.040s	1516.043us	1	1	100.00
	adc_ctrl_same_csr_outstanding	12.460s	4693.679us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	22.500s	7438.370us	5	5	100.00
	adc_ctrl_tl_intg_err	26.550s	8356.530us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	26.550s	8356.530us	25	25	100.00

2/10 passed

20.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	10	20.00
	adc_ctrl_stress_all_with_rand_reset	20.770s	9768.630us	2	10	20.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				97 test runs
	adc_ctrl_filters_polled	45855020439948616544383023250348341541871887469212115934234799136949057259283	393	UVM_INFO @ 313460472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	36182173392651977025389313236452985977964489638586265335255668750574219766763	393	UVM_INFO @ 399514159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	92929029467235212698917127851365052622310162413796473881324401778145132631011	393	UVM_INFO @ 361105073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	57544296315918122268925001591337424605319982979807217261664225146791847921473	393	UVM_INFO @ 328032987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	63753386748495142875394879762512124688138059039656910859668548175129950104716	393	UVM_INFO @ 283943021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	84172503313944376394019139827202788883029178222981806693471947894493957396732	393	UVM_INFO @ 402708624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	39275401281066056964600957896133167332612343497581840727746634451833112700309	393	UVM_INFO @ 510078249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	98741977847282607778604752778080112617486534974987530911719875922841581250415	393	UVM_INFO @ 386079793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	101134587265016003968701923266835140935799147787048445231740912185411510533258	481	UVM_INFO @ 35787418653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	62829772954446275756894970902167981927313033953543141230101776628905549461759	393	UVM_INFO @ 393080897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	26980006741760409657582212324645862707367295166417904804781664209304688603067	393	UVM_INFO @ 349576078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	43368697700282014032687828098225006665957415632011076440093787391962721069804	393	UVM_INFO @ 282446995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	98497858042166890436251740792931664096021224440177429872077204691237186802135	393	UVM_INFO @ 514420156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	15861015636114343522338186035178376777734662446506082507158263464922256709283	393	UVM_INFO @ 329064360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	21287466510053897946342724232699030925314220648106367461383548099389035114582	388	UVM_INFO @ 513511589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	112998198374199025984358615879583779917546620458634756402333415612871354739179	393	UVM_INFO @ 398563107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	81738877376330774385715550984419120371161909995941877367180840975971236969425	393	UVM_INFO @ 279681220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	15137465074890454161552075408550846298250735015301054035272560412236855474432	408	UVM_INFO @ 912830997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	115368988208214699259330928321715754552137369576369547161192845635714589356821	402	UVM_INFO @ 1085817528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	64339444668057562008021570533617588876250522015074107659759078847531143618392	393	UVM_INFO @ 472662801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	21273936770530224617036301197986395226403477437354502403836423066873353330475	393	UVM_INFO @ 369219431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	42526559164374362663612173563577456268686200398392211778019761114300314877849	393	UVM_INFO @ 334984698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	44477829914254290170181919400285648257440152801656143267660514025458133783569	393	UVM_INFO @ 407761134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	69991073052921202468319009383357674495614791615457146918101977361175039147251	388	UVM_INFO @ 409169361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	70578395244047027890274835836823397368276204021542842403003279330418999010796	388	UVM_INFO @ 284898833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	72232717002521421574981176687342075278162459857646436786075882249774366575856	393	UVM_INFO @ 308671876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	49404430054883720508223590351224309801127555308266915809066537629940544720273	393	UVM_INFO @ 513687950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	75997657047875525777122364607953745881370335420449107390768308268242293184564	415	UVM_INFO @ 859682016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	82271846488436712399534404747166400568637138210703100030691356368522635641118	391	UVM_INFO @ 6501050140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	22815901345853577379087037961740340139291593976250299224866386469674769665561	393	UVM_INFO @ 276558317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	62589305463005098455935995385143647976037258122193988631617099282033600032146	393	UVM_INFO @ 344286419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	19216776150997556697911913201522896554293669919922881178827582700852046941742	393	UVM_INFO @ 390879489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	17108489291755532796917200011382112865482940993134740403434281884096791785184	388	UVM_INFO @ 429519658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	58468804583675368227558059522704039179610220296997512662378139514333887426371	393	UVM_INFO @ 501185190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	6218402645165612395802593107846424950726536650457517364143559627475092990216	393	UVM_INFO @ 459096459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	83590702825976888856137460708994081676792675600939926073442646949875082538262	393	UVM_INFO @ 527880900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	15367596174104432206772611458622621320712013436061092295178983823345769194906	393	UVM_INFO @ 339924106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	89961640548491121933465156196949382948625147778370837743299409460951024227887	389	UVM_INFO @ 920946417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	92023557956140612814764219232200698175905639318809343869527990657166736412657	388	UVM_INFO @ 473945631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	85281215843152460006703909267238475933197731577739677438025898025875574940046	393	UVM_INFO @ 430027253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	34085997400269957452648830278736248748371614413078660008740503575835741568973	393	UVM_INFO @ 283904276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	28269458000052708964295826450183633488808308917240730422609918235349963220072	393	UVM_INFO @ 494238528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	76512134998386612753338271368605030903374708535838809397585047148518395302218	393	UVM_INFO @ 361163733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	18270986191300564946111065171824885102280222546418145099999155696633116644991	388	UVM_INFO @ 367586684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	71890791256756516898157382519409411739370642386998607686521939156252237558696	393	UVM_INFO @ 374124321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	96147087814313446594754485337110395640519495170614671955011673511749930341675	393	UVM_INFO @ 386415706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	23159436857888921284495054540140089557155811913678907015968451107590482266421	399	UVM_INFO @ 794669636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	85032833986269723625750325145054259609708036396097571948483804969379477951808	456	UVM_INFO @ 26390696153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	2868777508387473262791310240467521831951851692926717644577071472439324614171	393	UVM_INFO @ 324404856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	83031147995787146238143054115153766228357617389705493666607283793464048032363	393	UVM_INFO @ 370626553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	79313657466888340267215342555369584681397640200545028044079768830556075587804	393	UVM_INFO @ 405768047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	100819543070452862933294666066562350622538336450501013419036424197937731644970	393	UVM_INFO @ 380522691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	107881366145627795603156210982561077438812930103736762858175287048100734945362	393	UVM_INFO @ 410826281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	79377165670794665984860100469770983508387831758617722637137111518914787970597	393	UVM_INFO @ 417959828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	39622956644498150263088944973933440205743911922669773436110716886430678728193	393	UVM_INFO @ 341453026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	85398222723054509933251427655875046792386333848139896888037470616952867084030	393	UVM_INFO @ 459469611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	34229525370101015821188618849981276015890787868182921434520226406106090638704	445	UVM_INFO @ 5377057108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	68445668429760439365044180493336208238373780997868384950279403570215976280473	393	UVM_INFO @ 415273231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	102787282504508872050901146209703001543768567348127503619916863793709947049425	393	UVM_INFO @ 384634695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	88286598866491317004834006929470333707934091797043881698275427825275757847534	393	UVM_INFO @ 497274968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	85135725288723777981510692958244617470531631425864564086151804127893773156498	393	UVM_INFO @ 411787701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	32376043238853250513147126761135662500634692037287241016205365009030938204301	393	UVM_INFO @ 294301211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	11232947864520131286558454309104352563679022268805659985498140859190343186897	393	UVM_INFO @ 527218633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	105123457354922968413079925692624842596055752399684312929103854935075147455544	393	UVM_INFO @ 391993699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	13174519014231357121021844088050392006229023761472093947956831295100344918645	393	UVM_INFO @ 476764636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	51998506801149818632481516889231660968230138986237493441388731332375168256213	441	UVM_INFO @ 2019858555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	83994252172240568384742403530875329219700669040241783729117561361221160324970	496	UVM_INFO @ 43189014710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	7039219272365520502687506718556353173644091210042134646882662699257312587754	393	UVM_INFO @ 286013025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	109754487802551257213707375680110203986022067240345182707255499893358666674437	393	UVM_INFO @ 451286444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	70835423058481855870231925104593631667979056009991116821863581346678122325192	393	UVM_INFO @ 276380162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	78834206318420905004557747500033046666672589318876566007111864212494636671960	393	UVM_INFO @ 428689428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	71621157802852537742300708045211568568956772949812461143808536232326051261684	393	UVM_INFO @ 391586329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	74001836354828465141752860193519786693656111925340698628679631115404215748751	393	UVM_INFO @ 455548483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	67902383948641837870047934942485032981422159904723967977035866957027576756612	393	UVM_INFO @ 336652043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	37218914804130694820111069495880624988367671683487608782804876991610712853770	393	UVM_INFO @ 489201693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	103574523485982623132570586008473039687816855625365494834118666723256901666033	407	UVM_INFO @ 2857010357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	21361116640203157797860532274076939354492961821605369751561571669788332478831	389	UVM_INFO @ 801849106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	22326866478219540951021937450475412153427942080591347406168790801428155013489	393	UVM_INFO @ 389803784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	30364614214271539202024953857841499116265631724434227967924241657592185296438	393	UVM_INFO @ 476732329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	37817270281168272464651464570638083997470819506112558728988060682052908076873	393	UVM_INFO @ 298260299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	43446667599438092737729927194530500582514937679131029724006546392091310572109	393	UVM_INFO @ 322079466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	52221159565082370705645463888769468523681913056917596649704780127132299707301	393	UVM_INFO @ 325248354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	56729737963384832523545218794680579194005677960876661107868479372734422669429	393	UVM_INFO @ 381639467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	83265188057676984591962853070678912769451054321559942439849639297583068998293	393	UVM_INFO @ 383402535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	24953669725318640208983531712367887069463008331108101763657197628752797289562	393	UVM_INFO @ 282381826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	106138186657366275948109037246443026090217535500493872767411605741993061683390	407	UVM_INFO @ 1652888510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	20522326300874767193801964770075175589629816845368713143050726201551596537240	389	UVM_INFO @ 694147367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	20637793874227234431874955853790597835542058093985405429399840455877319278509	393	UVM_INFO @ 463265495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	79569777783581168487449424517975368914578563943450894256441053170383002522786	393	UVM_INFO @ 319110791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	64625032443977534195008482002629190152741749728595681917864234091808256854748	393	UVM_INFO @ 404227246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	71702221363323103945823543073735966947395232984294061268519569140078518442190	393	UVM_INFO @ 446461496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	108114126967891057016641556009998845234824443677888700745406452016545882362460	393	UVM_INFO @ 435410646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	46241311839251630923843669834813020113254873737987278749798204323976176693446	393	UVM_INFO @ 342662947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	106611063662728295674959488922139290169832636341957032742466876769203744824961	388	UVM_INFO @ 499949404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	37731359781674322961690460273423450517317657891714282884608863655766752273864	393	UVM_INFO @ 466556370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	92744967370956423069507189891949769426459505694896786264097329658335128393309	479	UVM_INFO @ 5034109805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	7513619234797623305075750931184805288572726157878196079640454012309915831266	389	UVM_INFO @ 595397367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---