Simulation Results

Simulation Results: aes/masked

15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: xcelium [unknown]

Coverage statistics

Total
97.37 %

code
96.62 %

assert
98.38 %

func
97.10 %

block
96.98 %

line
98.01 %

branch
92.69 %

toggle
97.99 %

FSM
97.78 %

Validation stages

V1		100.00%
V2		99.54%
V2S		96.02%
V3		20.00%

24/24 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	aes_wake_up	2.000s	68.219us	1	1	100.00
smoke				10	10	100.00
	aes_smoke	13.000s	507.062us	10	10	100.00
csr_hw_reset				1	1	100.00
	aes_csr_hw_reset	15.000s	66.848us	1	1	100.00
csr_rw				5	5	100.00
	aes_csr_rw	10.000s	84.009us	5	5	100.00
csr_bit_bash				1	1	100.00
	aes_csr_bit_bash	23.000s	187.329us	1	1	100.00
csr_aliasing				1	1	100.00
	aes_csr_aliasing	26.000s	90.777us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	aes_csr_mem_rw_with_rand_reset	13.000s	61.705us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	aes_csr_rw	10.000s	84.009us	5	5	100.00
	aes_csr_aliasing	26.000s	90.777us	1	1	100.00

217/218 passed

99.54 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
algorithm				70	70	100.00
	aes_smoke	13.000s	507.062us	10	10	100.00
	aes_config_error	31.000s	79.824us	50	50	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
key_length				70	70	100.00
	aes_smoke	13.000s	507.062us	10	10	100.00
	aes_config_error	31.000s	79.824us	50	50	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
back2back				35	35	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
	aes_b2b	50.000s	250.880us	25	25	100.00
backpressure				10	10	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
multi_message				94	95	98.95
	aes_smoke	13.000s	507.062us	10	10	100.00
	aes_config_error	31.000s	79.824us	50	50	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
	aes_alert_reset	34.000s	138.934us	24	25	96.00
failure_test				84	85	98.82
	aes_man_cfg_err	3.000s	60.579us	10	10	100.00
	aes_config_error	31.000s	79.824us	50	50	100.00
	aes_alert_reset	34.000s	138.934us	24	25	96.00
trigger_clear_test				10	10	100.00
	aes_clear	31.000s	128.675us	10	10	100.00
nist_test_vectors				1	1	100.00
	aes_nist_vectors	9.000s	487.742us	1	1	100.00
reset_recovery				24	25	96.00
	aes_alert_reset	34.000s	138.934us	24	25	96.00
stress				10	10	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
sideload				20	20	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
	aes_sideload	8.000s	108.468us	10	10	100.00
deinitialization				10	10	100.00
	aes_deinit	6.000s	342.759us	10	10	100.00
stress_all				10	10	100.00
	aes_stress_all	147.000s	7045.620us	10	10	100.00
alert_test				10	10	100.00
	aes_alert_test	31.000s	56.489us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	aes_tl_errors	4.000s	1596.344us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	aes_tl_errors	4.000s	1596.344us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	aes_csr_hw_reset	15.000s	66.848us	1	1	100.00
	aes_csr_rw	10.000s	84.009us	5	5	100.00
	aes_csr_aliasing	26.000s	90.777us	1	1	100.00
	aes_same_csr_outstanding	3.000s	140.596us	5	5	100.00
tl_d_partial_access				12	12	100.00
	aes_csr_hw_reset	15.000s	66.848us	1	1	100.00
	aes_csr_rw	10.000s	84.009us	5	5	100.00
	aes_csr_aliasing	26.000s	90.777us	1	1	100.00
	aes_same_csr_outstanding	3.000s	140.596us	5	5	100.00

V2S

941/980 passed

96.02 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reseeding				10	10	100.00
	aes_reseed	7.000s	330.830us	10	10	100.00
fault_inject				629	660	95.30
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_cipher_fi	58.000s	10005.072us	342	350	97.71
shadow_reg_update_error				19	20	95.00
	aes_shadow_reg_errors	3.000s	513.515us	19	20	95.00
shadow_reg_read_clear_staged_value				19	20	95.00
	aes_shadow_reg_errors	3.000s	513.515us	19	20	95.00
shadow_reg_storage_error				19	20	95.00
	aes_shadow_reg_errors	3.000s	513.515us	19	20	95.00
shadowed_reset_glitch				19	20	95.00
	aes_shadow_reg_errors	3.000s	513.515us	19	20	95.00
shadow_reg_update_error_with_csr_rw				17	20	85.00
	aes_shadow_reg_errors_with_csr_rw	4.000s	257.174us	17	20	85.00
tl_intg_err				30	30	100.00
	aes_sec_cm	10.000s	784.380us	5	5	100.00
	aes_tl_intg_err	5.000s	1736.974us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	aes_tl_intg_err	5.000s	1736.974us	25	25	100.00
sec_cm_lc_escalate_en_intersig_mubi				24	25	96.00
	aes_alert_reset	34.000s	138.934us	24	25	96.00
sec_cm_main_config_shadow				19	20	95.00
	aes_shadow_reg_errors	3.000s	513.515us	19	20	95.00
sec_cm_gcm_config_shadow				19	20	95.00
	aes_shadow_reg_errors	3.000s	513.515us	19	20	95.00
sec_cm_main_config_sparse				141	145	97.24
	aes_smoke	13.000s	507.062us	10	10	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
	aes_alert_reset	34.000s	138.934us	24	25	96.00
	aes_core_fi	90.000s	10019.477us	97	100	97.00
sec_cm_gcm_config_sparse				157	160	98.12
	aes_config_error	31.000s	79.824us	50	50	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
	aes_core_fi	90.000s	10019.477us	97	100	97.00
sec_cm_aux_config_shadow				19	20	95.00
	aes_shadow_reg_errors	3.000s	513.515us	19	20	95.00
sec_cm_aux_config_regwen				20	20	100.00
	aes_readability	3.000s	64.951us	10	10	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
sec_cm_key_sideload				20	20	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
	aes_sideload	8.000s	108.468us	10	10	100.00
sec_cm_key_sw_unreadable				10	10	100.00
	aes_readability	3.000s	64.951us	10	10	100.00
sec_cm_data_reg_sw_unreadable				10	10	100.00
	aes_readability	3.000s	64.951us	10	10	100.00
sec_cm_key_sec_wipe				10	10	100.00
	aes_readability	3.000s	64.951us	10	10	100.00
sec_cm_iv_config_sec_wipe				10	10	100.00
	aes_readability	3.000s	64.951us	10	10	100.00
sec_cm_data_reg_sec_wipe				10	10	100.00
	aes_readability	3.000s	64.951us	10	10	100.00
sec_cm_data_reg_key_sca				10	10	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
sec_cm_key_masking				10	10	100.00
	aes_stress	6.000s	275.616us	10	10	100.00
sec_cm_main_fsm_sparse				9	10	90.00
	aes_fi	28.000s	1069.188us	9	10	90.00
sec_cm_main_fsm_redun				654	685	95.47
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_cipher_fi	58.000s	10005.072us	342	350	97.71
	aes_ctr_fi	24.000s	114.013us	25	25	100.00
sec_cm_cipher_fsm_sparse				9	10	90.00
	aes_fi	28.000s	1069.188us	9	10	90.00
sec_cm_cipher_fsm_redun				629	660	95.30
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_cipher_fi	58.000s	10005.072us	342	350	97.71
sec_cm_cipher_ctr_redun				342	350	97.71
	aes_cipher_fi	58.000s	10005.072us	342	350	97.71
sec_cm_ctr_fsm_sparse				9	10	90.00
	aes_fi	28.000s	1069.188us	9	10	90.00
sec_cm_ctr_fsm_redun				312	335	93.13
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_ctr_fi	24.000s	114.013us	25	25	100.00
sec_cm_ghash_fsm_sparse				9	10	90.00
	aes_fi	28.000s	1069.188us	9	10	90.00
sec_cm_ctrl_sparse				654	685	95.47
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_cipher_fi	58.000s	10005.072us	342	350	97.71
	aes_ctr_fi	24.000s	114.013us	25	25	100.00
sec_cm_main_fsm_global_esc				24	25	96.00
	aes_alert_reset	34.000s	138.934us	24	25	96.00
sec_cm_main_fsm_local_esc				654	685	95.47
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_cipher_fi	58.000s	10005.072us	342	350	97.71
	aes_ctr_fi	24.000s	114.013us	25	25	100.00
sec_cm_cipher_fsm_local_esc				654	685	95.47
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_cipher_fi	58.000s	10005.072us	342	350	97.71
	aes_ctr_fi	24.000s	114.013us	25	25	100.00
sec_cm_ctr_fsm_local_esc				312	335	93.13
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_ctr_fi	24.000s	114.013us	25	25	100.00
sec_cm_ghash_fsm_local_esc				9	10	90.00
	aes_fi	28.000s	1069.188us	9	10	90.00
sec_cm_data_reg_local_esc				629	660	95.30
	aes_fi	28.000s	1069.188us	9	10	90.00
	aes_control_fi	61.000s	0.000us	278	300	92.67
	aes_cipher_fi	58.000s	10005.072us	342	350	97.71

2/10 passed

20.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	10	20.00
	aes_stress_all_with_rand_reset	159.000s	20284.224us	2	10	20.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				13 test runs
	aes_control_fi	63997147210136818039288405508851818385533819900266832636131462003531680624038	None
	aes_control_fi	14718713672156798358538841434705286671362360750666721044831923378223004873252	None
	aes_control_fi	80949413353354426738679798176120730031353715260188779737461000935873264350278	None
	aes_control_fi	47070061419832090083991245722651733748879345756568890889915039373582772333170	None
	aes_control_fi	107848152864325467801697420109593873888982810444577834526597280521143873509203	None
	aes_control_fi	79829645657154345949689237060609445411924407484591728370986315515429026517557	None
	aes_control_fi	46546589153401512368637403096873659021198430907842855426735835863487996924301	None
	aes_control_fi	50439618052363375132124446006888521545370464461727491206961313317938592731025	None
	aes_control_fi	61778845168119420086019232859014457194219418389583103991764924403818255519661	None
	aes_control_fi	38161344332998920939285402720058887739374414168946702502388583281662484051399	None
	aes_control_fi	22247272102455831114770849747986034795328427355911053445784900689624336733956	None
	aes_control_fi	60732352199999908734665800843940947355351443774711087706860311510312965891475	None
	aes_control_fi	83996445200688185493162019425965806486997579021860284622275484286423600052164	None
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!				9 test runs
	aes_control_fi	40676040756282730850424786439702641467539579926371371321105235307801955811240	147	UVM_INFO @ 10013132293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	7819848102807749143323091084194383535193731641894470848064286172941793247382	145	UVM_INFO @ 10011221408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	85676280711327849076943197571596039363837229949580158974976850346756048608594	145	UVM_INFO @ 10004638529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	62242269236326609935713871968197158805135309682887873378241409299435054048653	141	UVM_INFO @ 10032511389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	94419191500295241716244486688628322668199404859067135273346342665809319650036	149	UVM_INFO @ 10015768060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	33797831117537542197075830171061009314322565851939487401729895131398720697498	148	UVM_INFO @ 10086194325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	108274133098021016970057249324645728425978325634350794219664547289225128634938	145	UVM_INFO @ 10013093102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	112669703920809972531119614725614193572615196462162801367423577920210359381695	144	UVM_INFO @ 10013385065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	115018534639631645119750364493949524609785174888919795742937862069871229772688	140	UVM_INFO @ 10006669560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!				8 test runs
	aes_cipher_fi	45453523411686578964938402515060953679269416139764236816936374321437748168562	153	UVM_INFO @ 10017227127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	50203880927288294965853172404794394021322043580202493836147266584387437072818	145	UVM_INFO @ 10005071671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	94952197172828844515635704550429213490211048932814700247006952978983002472846	140	UVM_INFO @ 10004100914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	53401018848825439233559689152487467883217388842661761584114252989324629185810	151	UVM_INFO @ 10011855008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	107385137620061796069375166089588674827890684172653048401569966506638939782712	147	UVM_INFO @ 10027064503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	42054544998078369133383771831137497863008124751052351375558189809373615666674	148	UVM_INFO @ 10019749724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	37930356214688446280512283783830928078931037393570226643096753249690467725190	157	UVM_INFO @ 10032722221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	58710945187885236823953103791625954500702022818501252985000625618485030150710	147	UVM_INFO @ 10069733921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				3 test runs
	aes_stress_all_with_rand_reset	73474991452377156113988057381617816011778074611618332099017626662763571828453	149	UVM_INFO @ 137088018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	222144629895958022415112000427442902584120022427515011111411013842713285358	2362	UVM_INFO @ 3173454450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	111792803448501268420025165102489454970200229590606069658588532251168220658868	625	UVM_INFO @ 589539921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)				3 test runs
	aes_stress_all_with_rand_reset	31143620915390517519015454662559660245742801077171412465457917251063866364026	1416	UVM_INFO @ 1821625285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	17266063797986694750999530894682161039625799080391707488371054929115707266059	601	UVM_INFO @ 2258835939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	73571531583667382268400972044193192837878918474815002478756573247832519973012	1899	UVM_INFO @ 2082841308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [] vs []) Regname: aes_reg_block_extended.ctrl_shadowed reset value:				3 test runs
	aes_shadow_reg_errors_with_csr_rw	44040343702028634478351624244036705063571308148042221577023942138517391226614	106	UVM_INFO @ 199120920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_shadow_reg_errors_with_csr_rw	39370394975113250028826512733156515321056021779640111139542176281474381143019	106	UVM_INFO @ 62940823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_shadow_reg_errors	36429046486807277730520652285984933957631181380112264959891361254169871727604	106	UVM_INFO @ 31035183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!				2 test runs
	aes_core_fi	89531774014085084269980163478184479698267638320619243277490769506332772137026	144	UVM_INFO @ 10019476834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	73277452339309244433965590007915494051758016804054686946875503201087853571799	143	UVM_INFO @ 10037185492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1331) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault does not trigger!				1 test run
	aes_shadow_reg_errors_with_csr_rw	112462955763829837117210488950934631753508989458260962302205207161240054955120	107	UVM_INFO @ 190926727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues				1 test run
	aes_stress_all_with_rand_reset	78473106068953969764491362150761762390107475258101644399313838402289516834787	973	UVM_INFO @ 1202668697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_fi_vseq.sv:95) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset				1 test run
	aes_fi	26448304893114542519691005386595032883554808729046505531788375096079900331503	6808	UVM_INFO @ 177249314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error				1 test run
	aes_alert_reset	65853907143967790008876019215023384035829272207884132653487725444223383412520	1007	UVM_INFO @ 78788741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)				1 test run
	aes_stress_all_with_rand_reset	66590745721081628555040778577891766369382578977057398299837089753937620696263	323	UVM_INFO @ 1137060155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred!				1 test run
	aes_core_fi	77896233911926057890796961652821019176812292015858230250518908726824844184880	140	UVM_INFO @ 10029328588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---